Design and implementation of digital controlled boost PFC converter under boundary conduction mode

Dynamic response of boost power factor correction (PFC) converter operating in continuous-conduction mode (CCM) is heavily influenced by low-bandwidth of voltage control loop. A novel tri-state boost PFC converter operating in pseudo-continuous-conduction mode (PCCM) is proposed in this paper. An additional degree of control-freedom introduced by a freewheeling switching control interval helps to achieve PFC control. A simple and fast voltage control loop can be used to maintain a constant output voltage. Furthermore, compared with boost PFC converter operating in conventional discontinuous-conduction mode (DCM), boost PFC converter operating in PCCM demonstrates greatly improved current handling capability with reduced current and voltage ripples. Analytical and simulation results of the tri-state boost PFC converter have been presented and compared with those of the boost PFC converter operating in conventional CCM and DCM. Simulation results show excellent dynamic performance of the tri-state boost PFC converter.

The operation of the two-phase interleaved CRM Boost power factor correction (PFC) converter with coupled inductors is analyzed in this paper. Since the equivalent inductance varies with the switching mode and duty cycle, the current mode control method should be adopted to achieve PFC rather than the voltage mode control. The switching frequency is derived, and the self inductance is discussed in term of the minimum switching frequency, which should be higher than 20 kHz to avoid acoustic noise. The design methodology of the coupled inductors is presented as well. Compared to the discrete inductors, the coupled inductor has small size and low copper usage, so the power density of the PFC converter can be increased.

This paper presents the design of a digital controller for a 600 W Boundary-Conduction-Mode (BCM) interleaved boost converter used in an ac-dc Power-Factor-Correction (PFC) power supply. The output voltage of a typical boost PFC rectifier contains a 2nd harmonic ripple. Therefore to achieve good power factor, the output voltage compensator must have a low bandwidth, in order to sufficiently attenuate this 2nd harmonic component. As a result, the output voltage can suffer from poor transient response, especially at low input voltage. In this paper, a small-signal model of the output voltage dynamics is derived, where it is shown the open-loop gain of the system decreases with low input voltage. As a result, the output voltage transient response also deteriorates at low levels of input voltage. This can lead to poor voltage transient response for boost PFC converters that are designed to have an operating input line voltage range from 85 to 265 V. Having poor output voltage transient response is undesirable as it can lead to high peak over shoot on the output capacitors, or even worse, lead to an output voltage tracking failure. To correct this behaviour, an adaptive digital voltage compensator is designed to change gain at low input voltage, to ensure the output voltage maintains good transient response. Finally, the derived small-signal analysis, and output voltage compensator performance are experimentally verified on a 600 W interleaved BCM converter.

Power Factor Correction (PFC) converter is a key component in modern switching power supplies, while high efficiency and high power density are the main goals of PFC converter. In this paper, taking a single-phase Boost circuit as an example, a PFC converter with 300 kHz switching frequency and 1 kW output power which is based on continuous inductor current (CCM) mode is designed to reduce the volume of the core component and improve the power density of the converter. The paper includes the detailed design of the boost inductor, the analysis of the loss of the inductor at high frequency operation and the loss of the PFC converter. Finite element analysis is used to verify that the winding loss can be reduced by taking multi-strand wire winding. New semiconductor devices CoolMOS and SiC are employed which can reduce the loss effectively. The experimental results are provided which demonstrate that the employ of SiC diode and multi-strand wire winding can enable enhanced performance on efficiency.

These A novel power factor correction (PFC) Converter employing zero voltage transition (ZVT) technique based boost topology is proposed in this paper. It operates at a fixed frequency while achieving zero voltage turn-on of the main switch and zero current turn-off of the boost diode. This is accomplished by employing resonant operation only during switch transitions. During the rest of the cycle, the resonant network is essentially removed from the circuit and converter operation is identical to its non-resonant counterpart. This technique increases the efficiency to 95% and power factor to 0.99. Soft switching of the diode also reduces EMI, an important system consideration.The principle of operation, theoretical analysis, simulation results and experimental results are presented. A prototype of 500 W is built to test the proposed topology. The input voltage is from 170 V rms to 230 V rms. The output voltage is 400 V. The operation frequency is 100 KHz.

Buck-buck/Boost power factor correction (PFC) converter is a great choice to compensate the inherent dead zones in the input current of buck PFC converter. However, whether the converter operates with traditional constant on-time control in critical conduction mode (CRM) or with conventional constant duty-cycle control in discontinuous conduction mode (DCM), the power factor (PF) is low, especially at low input voltage. Therefore, fixed on-time ratio control (FOTRC) and fixed duty-cycle ratio control (FDCRC) are proposed for CRM/DCM buck-buck/boost PFC converter to achieve high PF, respectively. Both control methods maximize PF over wide input voltage range by adjusting on-time or duty-cycle of buck/boost mode and buck mode. Compared with the traditional controls, the proposed control methods also have advantage of increasing efficiency. Furthermore, for improving dynamic response performance, smooth and rapid dynamic response control (SRDRC) is put forward, which can reduce the regulation time and output voltage overshoot/undershoot when the load or input voltage changes abruptly. In addition, the implementation circuits combining FOTRC/FDCRC and SRDRC are designed. Two prototypes have been built and tested in the lab to demonstrate the validity of the theoretical analysis.

In low‐voltage distribution systems, the increased penetration of power electronic devices leads to the decentralization of harmonic sources, which puts the sensitive loads or communication systems in the risk status. The conventional methods of point‐to‐point harmonic control are not applicable. In order to solve this problem without increasing additional investments, this paper focuses on mitigating the harmonic interference through the power factor correction (PFC) converter. Hence, a critical conduction mode (CRM) single‐phase boost PFC converter with adaptive harmonic compensation (AHC) control is proposed to reduce the harmonic interference at user side. Firstly, the feed‐forward control loop of a PFC converter is decoupled into the fundamental branch and harmonic branch to trace the harmonic interference and generate the compensation current. Then the compensation gain is designed by the compensation loop gain and compensation capacity of PFC converter. Meanwhile, the characteristics of the PFC converter are analyzed to study the effect of the AHC control on the active power transmission and output load, which can provide important support for the proposed method in application. Finally, a 160‐W experimental prototype is built to verify the effectiveness of the proposed AHC control.

In this paper, an improved Zero-Voltage-Transition (ZVT) two-cell interleaved boost Power Factor Correction (PFC) converter is proposed and investigated. A new auxiliary circuit is designed and added to two-cell interleaved boost converter to reduce the switching losses. Only one auxiliary switch is used in the active soft switching auxiliary circuit. The main advantage of this auxiliary circuit is that it not only provides ZVT in the boost switches but also provides soft switching in the auxiliary switch and passive diodes. Therefore, the switching losses of the converter can be reduced. Compared to the previous published soft switching interleaved boost converters, only one auxiliary switch is needed in the auxiliary unit, so the auxiliary unit and control circuit are simple. A 1kW, 50 kHz two-cell interleaved boost PFC converter with an improved ZVT auxiliary circuit has been simulated using average current control method and the results are presented. Simulation results show that the main switches, the auxiliary switch and passive diodes are operating under soft switching mode.

This manuscript deals about the configuration of a power factor correction (PFC) converter feeding a drive of brushless DC (BLDC) motor for medium and low power equipment. The front-end PFC converter working in discontinuous inductor current mode (DICM) is applied for regulating the DC link voltage and PFC is achieved inherently. The BLDC motor speed is adjusted by regulating the DC link voltage of voltage source inverter (VSI) feeding to motor. The DC link voltage of drive system is maintained by a single DC voltage actuator. A prototype is developed for evaluating the performances of anticipated drive for the speed control over a broad range. The performance of anticipated drive is also validated for its function at varying AC mains voltages (90V–265V). Test results for power quality (PQ) parameters are compared with restrictions of power quality standard IEC 61000-3-2.

In this paper, a digital-based pulse train (PT) control technique for a boost power factor correction (PFC) converter operating in a discontinuous conduction mode (DCM) is presented, which can achieve nearly unity power factor (PF) over a universal input voltage range. Different from traditional digital control techniques, which usually require complex arithmetic operations, the digital-based PT control technique only needs a simple operation. Besides, a DCM boost PFC converter with digital PT control can operate at a high switching frequency, which is less dependent on the processing speed of a digital controller. Thus, the proposed control strategy can be implemented with general purpose digital controllers, such as low-speed and low-cost microcontroller unit, for the DCM boost PFC converter where the cost is a focus. The operation principle of the digital PT controlled DCM boost PFC converter is analyzed. Experimental results are provided, which show that high PF and low input current total harmonic distortion can be maintained over a universal input voltage range of 90–264 V ac.

The three-level boost power factor correction (PFC) converter has advantages of lower inductor current ripple and lower switch withstanding voltage compared with the boost PFC converter. Interleaved pulsewidth modulation had been used in the multiphase boost PFC converter. In the literature, interleaved current sensorless control (ICSC) for the multiphase boost PFC converters had been proposed. In this paper, the behavior of the three-level boost PFC converter is first analyzed. The results show that three-level converter has the same average equation as the interleaved boost PFC converter. Then, ICSC is modified for the three-level boost PFC converter with considering the voltage imbalance and the zero-crossing current distortion. The proposed modified ICSC (MICSC) is implemented in a field-programmable gate array board. Simulation results and experimental results are also provided to validate the proposed MICSC.

Digital control of a boost power factor correction (PFC) converter requires sampling of the input current. As the input current contains a considerable amount of switching ripple and high frequency switching noise, the choice of the sampling instant is very important. To avoid aliasing without employing a (very) high sampling frequency, the sampling is synchronized with the pulse width modulation (PWM). Sampling algorithms employing this technique successfully reject the input current ripple but are not immune to the high frequency switching noise present on all sampled signals. Therefore, a new sampling algorithm, intended for center-based or symmetric PWM, is deduced with as most important features: switching noise immunity, straightforwardness, accurate measurement of the averaged input current and the need for only few processor cycles. The operating principle, design issues and a theoretical study of the input current error induced by the sampling algorithm due to sampling instant timing errors are derived. All theoretical results are validated experimentally by using a digitally controlled boost PFC converter switching at 50 kHz.

In order to further increase the power density of power factor correction (PFC) converter, a structure of passive integration is proposed by combining EMI filter and Boost inductor in one magnetic component for PFC converters in this paper.

Nowadays electric vehicles (EVs) are the most popular due to their cost-effectiveness and as an alternative to traditional petroleum fuel-based vehicles. When EV is charged from the utility grid conventional AC-DC converter act as a nonlinear load drawing peaky current from a supply and results in a very poor input power factor. The converter present at the input AC side which converts alternating current (AC) into direct current (DC), a crucial part of an electric car battery charging system, must have high efficiency. The topologies for use at the ac input side to convert ac into dc for EV battery charging are evaluated in this paper. The focus is on boost converter-based power factor correction converters, which provide excellent efficiency, good power factor, and affordable pricing. Traditional boost power factor correction converter, interleaved boost power factor correction converter, and bridgeless totem pole boost power factor correction converter are the topologies under investigation. The performance of all these topologies is simulated using Matlab/Simulink. All converters give the output of 400 V DC from a universal ac input voltage with a Total Harmonic Distortion (THD) percentage level that satisfies the IEEE Standards are provided with their simulation results.

The authors propose a simple and robust voltage controller to improve voltage dynamics in power factor corrected (PFC) converters. The conventional control of the PFC converters requires filtering of twice-the-line-frequency voltage ripples present on the DC bus voltage to reduce the total harmonic distortion (THD) in the input current. This filtering action significantly reduces the effective voltage regulation bandwidth, resulting in slow voltage dynamics. The proposed scheme cancels the voltage ripple on the DC bus voltage feedback path without any filtering action and thereby allows design of large bandwidth voltage control loop. This eliminates large overshoots and undershoots in output voltage during transients, which are prevalent in conventionally designed PFC converters. The controller design and implementation are described and simulation results are presented for single-phase boost PFC converter as well as single-phase voltage source PFC converter to demonstrate the feasibility of the proposed technique.