A Parallel GPU Implementation of SWIFFTX

In this paper we have developed a new scheduling algorithm that provides a decrease in dynamic power consumption through achieving components scheduling. The major idea of that algorithm is to amplify the latency of some components whenever it is feasible without negatively influencing the dependency constraints. For that purpose, we have decreased the frequency of the components clocks. Since frequency and power are inter-related, a decrease in frequency value will be followed by a decrease in power consumption. Our algorithm has been tested and has given an interesting gain in dynamic power.

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreased power consumption by approximately 90% for different processing corners. In addition, in this paper the proposed method was designed using Interpolation technique for purpose of promoting the performance as well as decreasing the class of Chip. The simulation results indicate that the power consumption for Interpolation technique was decreased by approximately 5% compared to the proposed method. On the other hand, we compare the results of the proposed convector with those of convertors frequently referred in other studies. The results show that the power consumption is considerably decreased, using the proposed method.

As the computation bottleneck in lattice-based cryptography (LBC), the polynomial multiplication based on number theoretic transform (NTT) has been continuously studied for flexible hardware implementations with high area-efficiency. This paper presents an area-efficient and configurable NTT-based polynomial multiplier (AC-PM) incorporating algorithmic and architectural level optimization techniques. For the core operation of polynomial multiplication, two low-complexity and fast modular multiplication algorithms are introduced with loose constraints of LBC-friendly primes. Based on the proposed algorithms, a reconfigurable processing element (RPE) is dedicatedly designed to execute all the operations in an NTT-based polynomial multiplication: NTT, inverse NTT (INTT), and coefficient-wise multiplication (CWM). The proposed AC-PM can be configured with different numbers of RPEs and supports various polynomial degrees without recompilation. Additionally, the dataflow complexity is greatly simplified. More importantly, to the best of our knowledge, the twiddle factors are reused, for the first time, to support both NTT and INTT with multiple polynomial degrees, which leads to increased flexibility of AC-PM with small overhead on hardware resource. FPGA implementation results demonstrate that the proposed AC-PM significantly outperforms the prior arts in both flexibility and area efficiency.

On the ions produced by a straight channel multiplier

A high-stretch positive temperature coefficient (PTC) surface heating textile (PTC-SHT) was fabricated using a composite of PTC powder and multiwall carbon nanotubes (MWCNTs). The PTC-SHT (heating area = 100 × 100 mm2) was produced by screen-printing the PTC-MWCNT composite paste onto a high-stretch textile with embroidered electrodes. Overall, the temperature increased to 56.1 °C with a power consumption of 5 W over 7 min. Subsequently, the surface temperature of the PTC-SHT remained constant despite the continued decrease in power consumption. This indicated that heating was accompanied by an increase in resistance of the PTC-SHT, which is typical of this process—i.e., heating to a constant temperature under a constant voltage over an extended period of time. In addition, 4.63 W power was required to heat the PTC-SHT surface from an external temperature of 5 to 45 °C in 10 min, after which stable low-temperature heat generation behavior was observed at a constant temperature of 50 °C, which was maintained over 40 min. In contrast, negative temperature coefficient (NTC) behavior has been observed in an NTC-SHT consisting of only MWCNTs, where a slow heating rate in the initial stage of power application and a continuous increase in surface temperature and power consumption were noted. The PTC-SHT consumed less power for heat generation than the NTC-SHT and exhibited rapid heating behavior in the initial stage of power application. The heat generation characteristics of the PTC-SHT were maintained at 95% after 100,000 cycles of 20% stretch–contraction testing, and the heating temperature remained uniformly distributed within ± 2 °C across the entire heating element. These findings demonstrated that an SHT with PTC characteristics is highly suitable for functional warm clothing applications that require low power consumption, rapid heating, stable warmth, and high durability.

This study proposes the optimization of a low-level assembly code to reconstruct the flux for a splitting flux Harten–Lax–van Leer (SHLL) scheme on high-end graphic processing units. The proposed solver is implemented using the weighted essentially non-oscillatory reconstruction method to simulate compressible gas flows that are derived using an unsteady Euler equation. Instructions in the low-level assembly code, i.e. parallel thread execution and instruction set architecture in compute unified device architecture (CUDA), are used to optimize the CUDA kernel for the flux reconstruction method. The flux reconstruction method is a fifth-order one that is used to process the high-resolution intercell flux for achieving a highly localized scheme, such as the high-order implementation of SHLL scheme. Many benchmarking test cases including shock-tube and four-shock problems are demonstrated and compared. The results show that the reconstruction method is computationally very intensive and can achieve excellent performance up to 5183 GFLOP/s, ∼66% of peak performance of NVIDIA V100, using the low-level CUDA assembly code. The computational efficiency is twice the value as compared with the previous studies. The CUDA assembly code reduces 26.7% calculation and increases 37.5% bandwidth. The results show that the optimal kernel reaches up to 990 GB/s for the bandwidth. The overall efficiency of bandwidth and computation performance achieves 127% of the predicted performance based on the HBM2-memory roofline model estimated by Empirical Roofline Tool.

Two plasma actuators facing each other (facing PA) can generate streamwise vortices by placing parallelly to the mainstream. However, the plasma interference in the facing PA is a problem because it has influence on the performance. In this study, the discharge field, the power consumption, and the flow field are examined for the facing PA with various distances of exposed electrodes, and the influence of plasma interference is discussed by comparing with the single PA. As a result, we found that the influence of plasma interference became significant when the distance between two exposed electrodes became shorter than threshold value. The interference leads to the restriction of plasma discharge propagation and the reduction of the discharge light emission. These effect in the discharge field results in the decrease in power consumption and body force.

This paper addresses the problem of power optimization of intellectual property (IP) digital macrocells in embedded control systems. With reference to the case study of an 8051-compliant microcontroller, first the IP cell is analyzed to highlight the main building blocks contributing to power consumption; then register transfer level (RTL) techniques such as state encoding, clock gating and operand isolation are applied to reduce dynamic power consumption. As final result, when implementing the original and the modified IP in submicron CMOS standard-cells technology, a considerable decrease of power consumption, up to 40%, is achieved at the expenses of limited area and timing overheads. Our custom clock gating is also compared to the automatic clock gating insertion performed by commercial CAD tools, proving its higher power optimization efficiency. The proposed approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the VHDL source code. Being technology and CAD independent, these architecture-level optimizations can be combined with other low-power techniques proposed in literature at different design levels.

The dependence of power consumption on baffle length, L, in vessels agitated by a dual Rushton turbine system was studied within the turbulent regime, and also in relation to the impeller spacing, ΔH. A dependence of varying strength could be observed. The presence of baffles in the agitated systems provided a stabilizing effect with regard to the dependence of the Newton number Ne on the Reynolds number Re. A sharp decrease in power consumption could be detected for baffle lengths L < 0.3 H, with H the liquid height in the vessel. The Newton number was not significantly affected by L in the range 0.3 H < L< 0.5 H. For L > 0.5 H a sharp increase in Ne with increasing L could be observed. The two Rushton turbines act independently at ΔH > 1.65 d, with d being the impeller diameter. As the baffle length decreased, an increased mutual interaction between the two impellers could be observed for a broad regime of ΔH/d values. Ne was not affected by ΔH for the unbaffled agitated systems studied.

A preliminary design for a broadband, multiple quantum well (MQW), distributed Bragg reflector (DBR), electronically tunable laser diode array has been developed for implementation into optical memory configurations. The proposed MQW DBR diode array and a waveguide hologram with a blazed grating and/or holographic diffraction grating will be integrated into a photonic random optical memory access (PROMAC) device. PROMAC is a low inertia, low power, sub-nanosecond, parallel (e.g. 64 bit wide), wavelength addressing device which exploits free space optical interconnects. The MQW DBR laser diode array will enhance the performance of PROMAC by offering advantages in speed, spectral resolution, holographic separation and scan efficiency. An increase in speed as well as a decrease in power consumption can also be realized. Thus, increased storage densities and faster access rates can be achieved.

In this paper, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating at subthreshold voltage, which is below the voltage that turns the transistors on and off. Even though the transistors are not actually switching as usual in this region, they are able to complete the computation by modulating the leakage current that passes through them, resulting in a 20-100x decrease in power consumption. Our hybrid FFT design partitions a sequential butterfly FFT architecture into two regions, namely memory banks and processing elements, such that the former runs at superthreshold and the latter in the subthreshold voltage region. For a given throughput, the number of parallel processing units and their supply voltage is determined such that the overall power consumption of the design is minimized. For a 1024 point FFT operation, our parallel design is able to deliver the same throughput as a serial design, while consuming 65% less power. We study the effectiveness of this method for a variable throughput application such as a sensor node switching between a low throughput and high throughput mode, e.g. when sensing an interesting event. We compare our method with other methods used for throughput scaling such as voltage scaling and clock scaling and find that our scaling method will last up to three times longer on battery power.KeywordsFast Fourier TransformWireless Sensor NetworkSupply VoltageProcessing ElementTotal Power ConsumptionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The paper analyses international practices of energy saving for train traction. It describes methods that allow decrease of power consumption. Russian practices of energy consumption for train traction are reviewed, as well as methods for determining the power consumption related to condition of track layout geometry. Best practices of evaluation of impact of profile elevation unevenness to the train traction energy consumption are presented. The calculations that allow matching the data on track geometry before and after track maintenance works are performed, and the convictions concerning cost reduction for train traction energy saving are developed.

Design of improved write and read performance 12T sram cell with leakage power control technique

Ternary content-addressable memory gives an address at the output after searching for the word that is provided at the input. The word ternary means that the said memory is capable of storing ‘X’ which represents the presence of ‘1’ as well as ‘0’. Gate-based area efficient TCAM (G-AETCAM) uses flip-flops as storing media in the form of storing as well as masking element. These flip-flops are millions in number in the latest FPGA devices and are used only 1% in implementing G-AETCAM of size 64×36. In this paper, we have initialized the flip-flops to some binary value (‘1’ or ‘0’). Technically, these flip-flops are made SET when we want to initialize it by ‘1’ and are made CLEAR if we need to store ‘0’ in the corresponding storing or masking element. The said algorithm of initialization is implemented successfully on Xilinx Virtex-6 FPGA for 64×36 configuration which resulted in 3.45% decrease in power consumption and 0.83% increase in speed of the whole architecture.

Post-quantum cryptography is considered to provide security against both traditional and quantum computer attacks. Dilithium is a digital signature algorithm that derives its security from the challenge of finding short vectors in lattices. It has been selected as one of the standardizations in the NIST post-quantum cryptography project. Hardware-software co-design is a commonly adopted implementation strategy to address various implementation challenges, including limited resources, high performance, and flexibility requirements. In this study, we investigate using compact instruction set extensions (ISEs) for Dilithium, aiming to improve software efficiency with low hardware overheads. To begin with, we propose tightly coupled accelerators that are deeply integrated into the RISC-V processor. These accelerators target the most computationally demanding components in resource-constrained processors, such as polynomial generation, Number Theoretic Transform (NTT), and modular arithmetic. Next, we design a set of custom instructions that seamlessly integrate with the RISC-V base instruction formats, completing the accelerators in a compact manner. Subsequently, we implement our ISEs in a chip design for the Hummingbird E203 core and conduct performance benchmarks for Dilithium utilizing these ISEs. Additionally, we evaluate the resource consumption of the ISEs on FPGA and ASIC technologies. Compared to the reference software implementation on the RISC-V core, our co-design demonstrates a remarkable speedup factor ranging from 6.95 to 9.96. This significant improvement in performance is achieved by incorporating additional hardware resources, specifically, a 35% increase in LUTs, a 14% increase in FFs, 7 additional DSPs, and no additional RAM. Furthermore, compared to the state-of-the-art approach, our work achieves faster speed performance with a reduced circuit cost. Specifically, the usage of additional LUTs, FFs, and RAMs is reduced by 47.53%, 50.43%, and 100%, respectively. On ASIC technology, our approach demonstrates 12, 412 cell counts. Our co-design provides a better tradeoff implementation on speed performance and circuit overheads.