Impact of Initialization on Gate-Based Area Efficient Ternary Content-Addressable Memory

In this paper we have developed a new scheduling algorithm that provides a decrease in dynamic power consumption through achieving components scheduling. The major idea of that algorithm is to amplify the latency of some components whenever it is feasible without negatively influencing the dependency constraints. For that purpose, we have decreased the frequency of the components clocks. Since frequency and power are inter-related, a decrease in frequency value will be followed by a decrease in power consumption. Our algorithm has been tested and has given an interesting gain in dynamic power.

A preliminary design for a broadband, multiple quantum well (MQW), distributed Bragg reflector (DBR), electronically tunable laser diode array has been developed for implementation into optical memory configurations. The proposed MQW DBR diode array and a waveguide hologram with a blazed grating and/or holographic diffraction grating will be integrated into a photonic random optical memory access (PROMAC) device. PROMAC is a low inertia, low power, sub-nanosecond, parallel (e.g. 64 bit wide), wavelength addressing device which exploits free space optical interconnects. The MQW DBR laser diode array will enhance the performance of PROMAC by offering advantages in speed, spectral resolution, holographic separation and scan efficiency. An increase in speed as well as a decrease in power consumption can also be realized. Thus, increased storage densities and faster access rates can be achieved.

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreased power consumption by approximately 90% for different processing corners. In addition, in this paper the proposed method was designed using Interpolation technique for purpose of promoting the performance as well as decreasing the class of Chip. The simulation results indicate that the power consumption for Interpolation technique was decreased by approximately 5% compared to the proposed method. On the other hand, we compare the results of the proposed convector with those of convertors frequently referred in other studies. The results show that the power consumption is considerably decreased, using the proposed method.

A high-stretch positive temperature coefficient (PTC) surface heating textile (PTC-SHT) was fabricated using a composite of PTC powder and multiwall carbon nanotubes (MWCNTs). The PTC-SHT (heating area = 100 × 100 mm2) was produced by screen-printing the PTC-MWCNT composite paste onto a high-stretch textile with embroidered electrodes. Overall, the temperature increased to 56.1 °C with a power consumption of 5 W over 7 min. Subsequently, the surface temperature of the PTC-SHT remained constant despite the continued decrease in power consumption. This indicated that heating was accompanied by an increase in resistance of the PTC-SHT, which is typical of this process—i.e., heating to a constant temperature under a constant voltage over an extended period of time. In addition, 4.63 W power was required to heat the PTC-SHT surface from an external temperature of 5 to 45 °C in 10 min, after which stable low-temperature heat generation behavior was observed at a constant temperature of 50 °C, which was maintained over 40 min. In contrast, negative temperature coefficient (NTC) behavior has been observed in an NTC-SHT consisting of only MWCNTs, where a slow heating rate in the initial stage of power application and a continuous increase in surface temperature and power consumption were noted. The PTC-SHT consumed less power for heat generation than the NTC-SHT and exhibited rapid heating behavior in the initial stage of power application. The heat generation characteristics of the PTC-SHT were maintained at 95% after 100,000 cycles of 20% stretch–contraction testing, and the heating temperature remained uniformly distributed within ± 2 °C across the entire heating element. These findings demonstrated that an SHT with PTC characteristics is highly suitable for functional warm clothing applications that require low power consumption, rapid heating, stable warmth, and high durability.

Two plasma actuators facing each other (facing PA) can generate streamwise vortices by placing parallelly to the mainstream. However, the plasma interference in the facing PA is a problem because it has influence on the performance. In this study, the discharge field, the power consumption, and the flow field are examined for the facing PA with various distances of exposed electrodes, and the influence of plasma interference is discussed by comparing with the single PA. As a result, we found that the influence of plasma interference became significant when the distance between two exposed electrodes became shorter than threshold value. The interference leads to the restriction of plasma discharge propagation and the reduction of the discharge light emission. These effect in the discharge field results in the decrease in power consumption and body force.

This paper addresses the problem of power optimization of intellectual property (IP) digital macrocells in embedded control systems. With reference to the case study of an 8051-compliant microcontroller, first the IP cell is analyzed to highlight the main building blocks contributing to power consumption; then register transfer level (RTL) techniques such as state encoding, clock gating and operand isolation are applied to reduce dynamic power consumption. As final result, when implementing the original and the modified IP in submicron CMOS standard-cells technology, a considerable decrease of power consumption, up to 40%, is achieved at the expenses of limited area and timing overheads. Our custom clock gating is also compared to the automatic clock gating insertion performed by commercial CAD tools, proving its higher power optimization efficiency. The proposed approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the VHDL source code. Being technology and CAD independent, these architecture-level optimizations can be combined with other low-power techniques proposed in literature at different design levels.

The dependence of power consumption on baffle length, L, in vessels agitated by a dual Rushton turbine system was studied within the turbulent regime, and also in relation to the impeller spacing, ΔH. A dependence of varying strength could be observed. The presence of baffles in the agitated systems provided a stabilizing effect with regard to the dependence of the Newton number Ne on the Reynolds number Re. A sharp decrease in power consumption could be detected for baffle lengths L < 0.3 H, with H the liquid height in the vessel. The Newton number was not significantly affected by L in the range 0.3 H < L< 0.5 H. For L > 0.5 H a sharp increase in Ne with increasing L could be observed. The two Rushton turbines act independently at ΔH > 1.65 d, with d being the impeller diameter. As the baffle length decreased, an increased mutual interaction between the two impellers could be observed for a broad regime of ΔH/d values. Ne was not affected by ΔH for the unbaffled agitated systems studied.

The SWIFFTX algorithm is one of the candidates of SHA-3 Hash Competition that uses the number theoretic transform (NTT). It has 256-byte input blocks and 65-byte output blocks. In this paper, a parallel implementation of the algorithm and particular techniques to make it faster on GPU are proposed. We target version 6.1 of NVIDIA®CUDA™compute architecture that employs an ISA (Instruction Set Architecture) called Parallel Thread Execution (PTX) which possesses special instrinsics, hence we modify the reference implementation for better results. Experimental results indicate almost 10x improvement in speed and 5 W decrease in power consumption per \(2^{16}\) hashes.

In this paper, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating at subthreshold voltage, which is below the voltage that turns the transistors on and off. Even though the transistors are not actually switching as usual in this region, they are able to complete the computation by modulating the leakage current that passes through them, resulting in a 20-100x decrease in power consumption. Our hybrid FFT design partitions a sequential butterfly FFT architecture into two regions, namely memory banks and processing elements, such that the former runs at superthreshold and the latter in the subthreshold voltage region. For a given throughput, the number of parallel processing units and their supply voltage is determined such that the overall power consumption of the design is minimized. For a 1024 point FFT operation, our parallel design is able to deliver the same throughput as a serial design, while consuming 65% less power. We study the effectiveness of this method for a variable throughput application such as a sensor node switching between a low throughput and high throughput mode, e.g. when sensing an interesting event. We compare our method with other methods used for throughput scaling such as voltage scaling and clock scaling and find that our scaling method will last up to three times longer on battery power.KeywordsFast Fourier TransformWireless Sensor NetworkSupply VoltageProcessing ElementTotal Power ConsumptionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

On the ions produced by a straight channel multiplier

The paper analyses international practices of energy saving for train traction. It describes methods that allow decrease of power consumption. Russian practices of energy consumption for train traction are reviewed, as well as methods for determining the power consumption related to condition of track layout geometry. Best practices of evaluation of impact of profile elevation unevenness to the train traction energy consumption are presented. The calculations that allow matching the data on track geometry before and after track maintenance works are performed, and the convictions concerning cost reduction for train traction energy saving are developed.

Design of improved write and read performance 12T sram cell with leakage power control technique

Several range reencoding schemes have been proposed to mitigate the effect of range expansion and the limitations of small capacity, large power consumption, and high heat generation of ternary content addressable memory (TCAM)-based packet classification systems. However, they all disregard the semantics of classifiers and therefore miss significant opportunities for space compression. In this paper, we propose new approaches to range reencoding by taking into account classifier semantics. Fundamentally different from prior work, we view reencoding as a topological transformation process from one colored hyperrectangle to another, where the color is the decision associated with a given packet. Stated another way, we reencode the entire classifier by considering the classifier's decisions rather than reencode only ranges in the classifier ignoring the classifier's decisions as prior work does. We present two orthogonal, yet composable, reencoding approaches: domain compression and prefix alignment. Our techniques significantly outperform all previous reencoding techniques. In comparison to prior art, our experimental results show that our techniques achieve at least five times more space reduction in terms of TCAM space for an encoded classifier and at least three times more space reduction in terms of TCAM space for a reencoded classifier and its transformers. This, in turn, leads to improved throughput and decreased power consumption.

Most applications nowadays require protection of their data from tampering to ensure secure transfer of information. At the same time, they need to be secured quickly and within available resources. In this paper, efficient hardware architecture has been designed and implemented for the Advanced Encryption Standard (AES) algorithm based on the Field Programmable Gate Array (FPGA) using High Level Language (HLL). The design focused on the optimal use of available resources, thus iterative looping architecture is suggested to minimize the hardware resources utilization and power consumption. The design is synthesized and simulated using Xilinx ISE 14.7 and ModelSim software, respectively. The implementation is compared with other previous works in terms of area, and power consumption. The results show that the proposed design achieves significant decrease in area (utilize 423 slices) and power consumption (3.68 W). The throughput reaches the value of 2457 Mbit/Sec implemented on Virtex-6 xc6vlx195t-3 of Xilinx device family. This makes the proposed design suitable for applications, where resources are limited.

Electrolyte-plasma treatment has become widespread in the industry as an alternative to traditional chemical, electrochemical and mechanical methods of improving the surface quality of products made of metallic materials. Advantages ofelectrolyte-plasma treatment are a high intensity of microroughness smoothing, the use of low concentration salts solutions as electrolytes, the possibility of processing products of complex shape. The main disadvantage of this method is high power consumption, so the method can be considered in its classical form to the power-consuming. A possible way of reducing power consumption is treatment in unsteady modes that arise in the transition zone between a switching and stable electrolyte-plasma treatment process and is characterized by the periodic formation of a stable vapor-gas shell and a transition to an electrochemical process. The paper presents the results of a study of the influence of a high-gradient electric field under unsteady electrolyte-plasma treatment modes on the energy parameters of the process and the characteristics of the surface being treated. It is established that a high-gradient electric field has a significant effect on the decrease in specific power consumption, which is explained by a decrease in losses in the electrolyte and the influence of the field on the formation and maintenance of the vapor-gas shell. As a result of the study of the effect of a high-gradient electric field in unsteady EPT modes on characteristics of the surface layer was established that a significant impulse current density in the zone of predominantly electrochemical treatment leads to a selective etching of the surface and the formation of a characteristic micro relief of the surface with a developed porous microstructure with pore sizes from 0.3 to 2.5 microns. The most pronounced porous microstructure is provided at a voltage of 270–300 V and an additional inductance of 3.2 mH.