Scheduling algorithm for digital systems to optimize dynamic power

This paper addresses the problem of power optimization of intellectual property (IP) digital macrocells in embedded control systems. With reference to the case study of an 8051-compliant microcontroller, first the IP cell is analyzed to highlight the main building blocks contributing to power consumption; then register transfer level (RTL) techniques such as state encoding, clock gating and operand isolation are applied to reduce dynamic power consumption. As final result, when implementing the original and the modified IP in submicron CMOS standard-cells technology, a considerable decrease of power consumption, up to 40%, is achieved at the expenses of limited area and timing overheads. Our custom clock gating is also compared to the automatic clock gating insertion performed by commercial CAD tools, proving its higher power optimization efficiency. The proposed approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the VHDL source code. Being technology and CAD independent, these architecture-level optimizations can be combined with other low-power techniques proposed in literature at different design levels.

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreased power consumption by approximately 90% for different processing corners. In addition, in this paper the proposed method was designed using Interpolation technique for purpose of promoting the performance as well as decreasing the class of Chip. The simulation results indicate that the power consumption for Interpolation technique was decreased by approximately 5% compared to the proposed method. On the other hand, we compare the results of the proposed convector with those of convertors frequently referred in other studies. The results show that the power consumption is considerably decreased, using the proposed method.

A high-stretch positive temperature coefficient (PTC) surface heating textile (PTC-SHT) was fabricated using a composite of PTC powder and multiwall carbon nanotubes (MWCNTs). The PTC-SHT (heating area = 100 × 100 mm2) was produced by screen-printing the PTC-MWCNT composite paste onto a high-stretch textile with embroidered electrodes. Overall, the temperature increased to 56.1 °C with a power consumption of 5 W over 7 min. Subsequently, the surface temperature of the PTC-SHT remained constant despite the continued decrease in power consumption. This indicated that heating was accompanied by an increase in resistance of the PTC-SHT, which is typical of this process—i.e., heating to a constant temperature under a constant voltage over an extended period of time. In addition, 4.63 W power was required to heat the PTC-SHT surface from an external temperature of 5 to 45 °C in 10 min, after which stable low-temperature heat generation behavior was observed at a constant temperature of 50 °C, which was maintained over 40 min. In contrast, negative temperature coefficient (NTC) behavior has been observed in an NTC-SHT consisting of only MWCNTs, where a slow heating rate in the initial stage of power application and a continuous increase in surface temperature and power consumption were noted. The PTC-SHT consumed less power for heat generation than the NTC-SHT and exhibited rapid heating behavior in the initial stage of power application. The heat generation characteristics of the PTC-SHT were maintained at 95% after 100,000 cycles of 20% stretch–contraction testing, and the heating temperature remained uniformly distributed within ± 2 °C across the entire heating element. These findings demonstrated that an SHT with PTC characteristics is highly suitable for functional warm clothing applications that require low power consumption, rapid heating, stable warmth, and high durability.

Two plasma actuators facing each other (facing PA) can generate streamwise vortices by placing parallelly to the mainstream. However, the plasma interference in the facing PA is a problem because it has influence on the performance. In this study, the discharge field, the power consumption, and the flow field are examined for the facing PA with various distances of exposed electrodes, and the influence of plasma interference is discussed by comparing with the single PA. As a result, we found that the influence of plasma interference became significant when the distance between two exposed electrodes became shorter than threshold value. The interference leads to the restriction of plasma discharge propagation and the reduction of the discharge light emission. These effect in the discharge field results in the decrease in power consumption and body force.

The dependence of power consumption on baffle length, L, in vessels agitated by a dual Rushton turbine system was studied within the turbulent regime, and also in relation to the impeller spacing, ΔH. A dependence of varying strength could be observed. The presence of baffles in the agitated systems provided a stabilizing effect with regard to the dependence of the Newton number Ne on the Reynolds number Re. A sharp decrease in power consumption could be detected for baffle lengths L < 0.3 H, with H the liquid height in the vessel. The Newton number was not significantly affected by L in the range 0.3 H < L< 0.5 H. For L > 0.5 H a sharp increase in Ne with increasing L could be observed. The two Rushton turbines act independently at ΔH > 1.65 d, with d being the impeller diameter. As the baffle length decreased, an increased mutual interaction between the two impellers could be observed for a broad regime of ΔH/d values. Ne was not affected by ΔH for the unbaffled agitated systems studied.

A preliminary design for a broadband, multiple quantum well (MQW), distributed Bragg reflector (DBR), electronically tunable laser diode array has been developed for implementation into optical memory configurations. The proposed MQW DBR diode array and a waveguide hologram with a blazed grating and/or holographic diffraction grating will be integrated into a photonic random optical memory access (PROMAC) device. PROMAC is a low inertia, low power, sub-nanosecond, parallel (e.g. 64 bit wide), wavelength addressing device which exploits free space optical interconnects. The MQW DBR laser diode array will enhance the performance of PROMAC by offering advantages in speed, spectral resolution, holographic separation and scan efficiency. An increase in speed as well as a decrease in power consumption can also be realized. Thus, increased storage densities and faster access rates can be achieved.

The SWIFFTX algorithm is one of the candidates of SHA-3 Hash Competition that uses the number theoretic transform (NTT). It has 256-byte input blocks and 65-byte output blocks. In this paper, a parallel implementation of the algorithm and particular techniques to make it faster on GPU are proposed. We target version 6.1 of NVIDIA®CUDA™compute architecture that employs an ISA (Instruction Set Architecture) called Parallel Thread Execution (PTX) which possesses special instrinsics, hence we modify the reference implementation for better results. Experimental results indicate almost 10x improvement in speed and 5 W decrease in power consumption per \(2^{16}\) hashes.

In this paper, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating at subthreshold voltage, which is below the voltage that turns the transistors on and off. Even though the transistors are not actually switching as usual in this region, they are able to complete the computation by modulating the leakage current that passes through them, resulting in a 20-100x decrease in power consumption. Our hybrid FFT design partitions a sequential butterfly FFT architecture into two regions, namely memory banks and processing elements, such that the former runs at superthreshold and the latter in the subthreshold voltage region. For a given throughput, the number of parallel processing units and their supply voltage is determined such that the overall power consumption of the design is minimized. For a 1024 point FFT operation, our parallel design is able to deliver the same throughput as a serial design, while consuming 65% less power. We study the effectiveness of this method for a variable throughput application such as a sensor node switching between a low throughput and high throughput mode, e.g. when sensing an interesting event. We compare our method with other methods used for throughput scaling such as voltage scaling and clock scaling and find that our scaling method will last up to three times longer on battery power.KeywordsFast Fourier TransformWireless Sensor NetworkSupply VoltageProcessing ElementTotal Power ConsumptionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

On the ions produced by a straight channel multiplier

The paper analyses international practices of energy saving for train traction. It describes methods that allow decrease of power consumption. Russian practices of energy consumption for train traction are reviewed, as well as methods for determining the power consumption related to condition of track layout geometry. Best practices of evaluation of impact of profile elevation unevenness to the train traction energy consumption are presented. The calculations that allow matching the data on track geometry before and after track maintenance works are performed, and the convictions concerning cost reduction for train traction energy saving are developed.

Design of improved write and read performance 12T sram cell with leakage power control technique

Ternary content-addressable memory gives an address at the output after searching for the word that is provided at the input. The word ternary means that the said memory is capable of storing ‘X’ which represents the presence of ‘1’ as well as ‘0’. Gate-based area efficient TCAM (G-AETCAM) uses flip-flops as storing media in the form of storing as well as masking element. These flip-flops are millions in number in the latest FPGA devices and are used only 1% in implementing G-AETCAM of size 64×36. In this paper, we have initialized the flip-flops to some binary value (‘1’ or ‘0’). Technically, these flip-flops are made SET when we want to initialize it by ‘1’ and are made CLEAR if we need to store ‘0’ in the corresponding storing or masking element. The said algorithm of initialization is implemented successfully on Xilinx Virtex-6 FPGA for 64×36 configuration which resulted in 3.45% decrease in power consumption and 0.83% increase in speed of the whole architecture.

A parallel 4D fMRI filtering algorithm is proposed to overcome the bottlenecks of large 4D volumetric fMRI data and its overlapping segments by input decimation, multidimensional intensive computation by parallel processing and the boundary conditions by output interpolation. Three spatial convolution architectures implement this parallel multidimensional filtering algorithm in Virtex-6 FPGA board, as automated 4D fMRI filtering systems. These three automated filtering systems are devised as “plug and develop” processors to filter any 4D volumetric data. Then, two sets of generic Edge and noise smoothing filtering operators are prototypically plugged and developed to be improved for filtering a dementia case study of color 256 × 256 × 4 × 3 volumetric fMRI. Accordingly, performance indices of the three architectures are evaluated as a complete package of area, speed, dynamic power, and throughput. Significant improvements have been achieved in keeping a stable speed, decreasing power consumption and increasing throughput in color fMRI filtering applications. All three architectures have an operating (225 MHz) maximum frequency. The power consumption improved more than two-fold using architecture 2 compared to 3. The highest throughput is achieved by architectures 2 and 3 almost (2.5) times than that of architecture 1. Evidently, all three architectures are performance-aware processors, and architecture 2 is optimal.

In todaypsilas technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.

A fully power aware globally asynchronous locally synchronous network-on-chip circuit is presented in this paper. The circuit is arranged around an asynchronous network-on-chip providing a 17 Gbits/s throughput and automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each NoC units. The dynamic power consumption can be reduced up to a factor of 8 while the static power consumption is reduced by 2 decades in stand-by mode.