A parameterized graph-based framework for high-level test synthesis

Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iteration, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits. The topics covered in this paper include an overview of HLS and testability parameters, our testability model and experimental results.

With the development of fabrication, the capacities of application-specific integrated circuits (ASICs) that implement data-intensive applications are increasing as well. in high-level view, the results of functional units (FUs) and register allocation have a significant impact on power, thermal, area and timing etc., especially for data-dominated behaviors. Techniques for power minimization might be applied in different levels of the design hierarchy, but high-level synthesis (HLS) has attracted a special attention due to its inherent ability of better design space exploration. All kinds of methods for register optimization are presented in the recent past. This paper presents a new simultaneous FUs and register allocation method, which combining heuristic list scheduling algorithm and left-edge algorithm to optimize register number and power. From the experimental results, it shows that different FUs allocation results deliver an average 1.83 reduction in register number. And compared with traditional allocation method, we can obtain a 5.81% reduction in power consumption. In order to optimize area with the design demand, it will be at the expense of power dissipation, our design method also can achieve power-area balance.

The authors propose design for testability at the logic synthesis level. Their state assignment is aimed at producing a reduced feedback or pipeline like structure which is easily analyzed by a sequential circuit test generator. State variables are assigned one at a time such that a state variable depends only on primary inputs and the previously assigned state variables. This results in a purely pipeline structure for finite-memory or definite machines. For other machines, the number of cycles in the implemented structure is minimized. The authors give several examples to compare their reduced feedback synthesis with another method that is aimed at reducing the amount of logic in a multilevel implementation. Results show a marked improvement in test generation time and fault coverage; in terms of logic their method did just as well as the other method. >

A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS '89 circuits have been generated and showed an improvement in test generation time and fault coverage.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

This paper presents a test synthesis technique for behavioral descriptions. The technique is guided by two testability metrics which quantify the controllability and observability of behavioral variables and structural signals. The method is based on utilizing redundant register transfers in the data path to produce a test behavior with better controllability and observability properties. This approach can avoid unnecessary insertions of test structures in the data path. A test scheme for conditional statements has been developed involving minimal changes in the controller. Our experimental results show improvements in fault coverage at modest hardware overhead.

Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.

Field-programmable gate arrays (FPGAs) can potentially be configured as beamforming platforms for ultrasound imaging, but a long design time and skilled expertise in hardware programming are typically required. In this article, we present a novel approach to the efficient design of FPGA beamformers for synthetic aperture (SA) imaging via the use of software-based high-level synthesis techniques. Software kernels (coded in OpenCL) were first developed to stage-wise handle SA beamforming operations, and their corresponding FPGA logic circuitry was emulated through a high-level synthesis framework. After design space analysis, the fine-tuned OpenCL kernels were compiled into register transfer level descriptions to configure an FPGA as a beamformer module. The processing performance of this beamformer was assessed through a series of offline emulation experiments that sought to derive beamformed images from SA channel-domain raw data (40-MHz sampling rate, 12 bit resolution). With 128 channels, our FPGA-based SA beamformer can achieve 41 frames per second (fps) processing throughput (3.44 × 10(8) pixels per second for frame size of 256 × 256 pixels) at 31.5 W power consumption (1.30 fps/W power efficiency). It utilized 86.9% of the FPGA fabric and operated at a 196.5 MHz clock frequency (after optimization). Based on these findings, we anticipate that FPGA and high-level synthesis can together foster rapid prototyping of real-time ultrasound processor modules at low power consumption budgets.

FPGA has emerged as one of the attractive computing devices in the post-Moore era because of its power efficiency and reconfigurability, even for future high-performance computing. We have designed an OpenACC compiler for FPGA to generate the kernel code by using stream processing Domain Specific Language (DSL) called SPGen, with OpenCL. Although, recently, the programming for FPGA has been improved dramatically by High-Level Synthesis (HLS) frameworks such as OpenCL and HLS C, yet it is still too difficult for HPC application developers, and the directive-based programming models such as OpenACC should be supported even for FPGA. OpenCL can be used as a portable intermediate code for OpenACC for FPGA. However, the generation of hardware from OpenCL is not easy to understand and therefore requires expert knowledge. SPGen is a DSL framework for generating stream processing HDL modules from the description of a dataflow graph. The advantage of our approach is that the code generation with SPGen enables more comprehensive low-level optimization in the OpenACC compiler. The preliminary evaluation results show that, for some kernels, the proposed method, which translates the OpenACC C code into OpenCL and SPGen codes, can perform optimization in the lower level more explicitly than the OpenCL-only method, which translates the OpenACC C code into the OpenCL code only. We also observed that more resources might be consumed in the proposed method. However, implementations of both methods are preliminary. We believe improving code generation will fix the problems such as high resource consumption.

This paper presents an efficient high-level synthesis (HLS) approach to improve RT-level concurrent testing. The proposed method used for both fault detection and fault location. At first the available resources are used in their dead intervals to test active resources for fault detection, and then some changes are applied to the RT-level controller to locate the faults. The fault detection step is based on a genetic algorithm (GA) search technique. This genetic algorithm is applied to the design after high level synthesis process to explore the test map. The proposed method has been evaluated based on dependability enhancement and area/latency overhead imposed to different benchmarks after applying our algorithm. The dependability has been considered in terms of fault coverage. The experimental result shows that applying our algorithm, the associated area overhead and performance penalty are negligible while the online fault coverage improvement is considerable.

This paper presents techniques to improve compressions by improving fault coverage that can be achieved by broadcast scan. Due to reconvergent gates that artificially occur in broadcast scan, broadcast scan fault coverage is often much lower than standard serial scan fault coverage. The proposed scan chain reordering technique improves broadcast scan fault coverage by minimizing the number of reconvergent gates and hence no or very small number of test patterns are required to be applied by standard serial scan to detect faults undetected by broadcast scan. This increases the overall compression ratio. To eliminate or minimize increase in routing overhead, the distance that each scan cell can be relocated by the scan chain reordering procedure is limited. Test points are inserted to further reduce correlation among outputs of scancells. The proposed scan chain reordering technique improved broadcast scan fault converge by up to 8.5%. Large fault coverage improvement was achieved by the proposed method, especially for circuits that suffer low broadcast scan fault coverage. Broadcast scan fault coverage for the largest two industrial designs was even higher than standard serial scan fault coverage.

Category:Ankle; Hindfoot; OtherIntroduction/Purpose:Peritalar subluxation (PTS) of the hindfoot is a critical finding in Progressive Collapsing Foot Deformity (PCFD). Subluxation of the middle facet and sinus tarsi impingement have recently been shown to represent essential markers of pronounced and potentially progressive deformity. Weightbearing CT (WBCT) imaging and three-dimensional (3D) distance (DM) and coverage maps (CM) allow a complete and accurate assessment of PTS markers across the entire peritalar surface. This prospective comparative study aimed to assess the effectiveness of joint-sparing realignment surgical treatment for flexible PCFD in reducing PTS and to correlate the improvement with patient-reported outcomes (PROs). We hypothesized that surgical treatment would significantly improve PTS markers, mainly decreasing sinus tarsi coverage/impingement and middle facet subluxation, and that this improvement would correlate with increased PROs.Methods:In this IRB-approved prospective and comparative study, we enrolled patients with flexible PCFD, no prior surgeries, and failed conservative treatment. Included patients (n=10, 7 females/3 males, mean age 57.2, range 37-74) underwent joint-sparing surgical realignment procedure by a single surgeon. Standing weightbearing CT (WBCT) was completed preoperatively and 3- months postoperatively. Following automatic bone segmentation, 3D distance maps (DMs) of the entire peritalar surface were generated, and coverage of the subtalar joint articular facets (anterior, middle, and posterior) and sinus tarsi were assessed as markers of PTS. Joint coverage was defined as the percentage of articular space where DMs were <5 mm. Coverage Maps (CM) were built highlighting areas of adequate joint interaction (blue), joint subluxation (pink), and impingement (red). PROs were evaluated preoperatively and at the latest follow-up. Differences between preop/postop measurements and PROs were assessed by independent t-tests/Wilcoxon and bivariate analysis. P-values <.05 were considered significant.Results:The overall follow-up was 8.2 months (6-13 months). Medial displacement calcaneal osteotomies, lateral column lengthening, and first ray realignment procedures (either Cotton osteotomy or Lapidus) were performed in all patients. Foot and Ankle Offset significantly improved from 10.6% preoperatively to 3.1% postoperatively (p=0.0005), on average. Significant averaged improvement was also observed in anterior facet joint coverage (61.6%), as well as a reduction in sinus tarsi coverage/impingement (-43.2%) (both p<0.001). Middle (19.5%, p=0.08) and posterior facet joint coverage (3.5%, p=0.06) also demonstrated improvements, however not significant. PROs improved significantly on average postoperatively, with the European Foot and Ankle Surgery (EFAS) Score increasing from 3.1 to 7.3 (p=0.02) and the Foot Function Index (FFI) improving from 71.5 to 48.7 (p=0.01). Improvements in EFAS scores and FFI significantly correlated with improvements in middle facet coverage (R2 0.89, p=0.0154) and anterior facet coverage (R2 0.80, p=0.04), respectively.Conclusion:Our study was the first to evaluate WBCT 3D distance mapping's role in the assessment of surgical correction of PTS in patients with PCFD. We found significant improvements in subtalar joint anterior facet coverage and sinus tarsi impingement following surgical reconstruction, with a trend to significant improvements in middle and posterior facet joint coverage. More importantly, improvements in middle and anterior facet coverage correlated significantly with improved PROs (EFAS score and FFI, respectively). Based on our study results, optimization of subtalar joint coverage and reduction of PTS should be goals of surgical treatment of PCFD patients.

Background: patients with rifampicin-resistant tuberculosis (RR-TB; including multidrug-resistance with added isoniazid resistance) require longer and more complex treatment than those with drug-susceptible disease. The global response to RR-TB will influence progress towards the post-2015 targets of the End TB Strategy of the World Health Organization (WHO). Methods: aggregated surveillance data reported annually by Member States allow WHO to monitor key indicators of the global RR-TB response, namely coverage of susceptibility testing, case detection, enrolment on treatment, and treatment success. Findings: about 340,000 RR-TB cases were estimated to occur among the pulmonary TB patients notified worldwide in 2014. While coverage of testing for RR-TB reached 12% of new and 58% of previously-treated TB cases notified that year, only 36% (122,618 patients) of estimated RR-TB cases were reported worldwide. In 2014, 110,803 TB patients were known to have started second-line TB treatment. Only 50% of RR-TB cases starting treatment in 2012 completed it successfully. Testing for RR-TB and treatment enrolments increased steadily over time, but case detection and treatment success remained at the same levels. Interpretation: improvements in coverage of testing and treatment for RR-TB are a result of the widespread roll-out of molecular diagnostics (e.g. Xpert MTB/RIF) and better access to second-line TB medication respectively. These efforts need to be stepped up and matched by a better identification of patients at risk of drug-resistance to be tested, more efficient capture of surveillance data and enhanced access to more effective regimens and social support for patients on treatment.

Testing and diagnosis techniques play a key role during the advance of semiconductor memory technologies. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and yield improvement. The test and diagnosis complexity are 12N for bit-oriented diagnosis algorithm, N is the number of addresses is proposed for fault detection and diagnosis. Using the proposed march-based algorithm (march-12N), 100% of the faults under the fault model are covered and partial distinguished. They also can locate the faulty cells and identify their types. The complete fault and diagnosis procedures for state coupling faults, idempotent coupling faults and inversion coupling faults are written in this paper. Therefore, all the coupling faults that occur in SRAM memories are verified and proved the valid results. Furthermore, the realistic 12N test and diagnosis algorithm has shown the improvement of diagnostic resolution and test time.

This paper presents a methodology to insert scan paths in a design that is specified on the Register Transfer Level (RT-Level). The results indicate that selecting registers on this level guarantees a reduction in DFT design time and improvement of fault coverage, without incurring high hardware overhead.