A test synthesis technique using redundant register transfers

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

This paper presents techniques to improve compressions by improving fault coverage that can be achieved by broadcast scan. Due to reconvergent gates that artificially occur in broadcast scan, broadcast scan fault coverage is often much lower than standard serial scan fault coverage. The proposed scan chain reordering technique improves broadcast scan fault coverage by minimizing the number of reconvergent gates and hence no or very small number of test patterns are required to be applied by standard serial scan to detect faults undetected by broadcast scan. This increases the overall compression ratio. To eliminate or minimize increase in routing overhead, the distance that each scan cell can be relocated by the scan chain reordering procedure is limited. Test points are inserted to further reduce correlation among outputs of scancells. The proposed scan chain reordering technique improved broadcast scan fault converge by up to 8.5%. Large fault coverage improvement was achieved by the proposed method, especially for circuits that suffer low broadcast scan fault coverage. Broadcast scan fault coverage for the largest two industrial designs was even higher than standard serial scan fault coverage.

A parameterized graph-based framework for high-level test synthesis

This paper presents a methodology to insert scan paths in a design that is specified on the Register Transfer Level (RT-Level). The results indicate that selecting registers on this level guarantees a reduction in DFT design time and improvement of fault coverage, without incurring high hardware overhead.

The authors propose design for testability at the logic synthesis level. Their state assignment is aimed at producing a reduced feedback or pipeline like structure which is easily analyzed by a sequential circuit test generator. State variables are assigned one at a time such that a state variable depends only on primary inputs and the previously assigned state variables. This results in a purely pipeline structure for finite-memory or definite machines. For other machines, the number of cycles in the implemented structure is minimized. The authors give several examples to compare their reduced feedback synthesis with another method that is aimed at reducing the amount of logic in a multilevel implementation. Results show a marked improvement in test generation time and fault coverage; in terms of logic their method did just as well as the other method. >

A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS '89 circuits have been generated and showed an improvement in test generation time and fault coverage.

Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.

A procedure proposed earlier for improving the fault coverage of a random primary input sequence modifies the input sequence so as to avoid repeated synchronization of state variables. We show that in addition to the values of state variables, it is also important to consider repeated setting of other lines to the same values. A procedure and experimental results are presented to demonstrate the improvements in fault coverage of random primary input sequences when the values of selected lines are considered.

This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST. Our goal is to arrange the system bistables into scan paths such that some of the BIST and scan logic is shared with the functional logic. Logic sharing is possible when scan dependence is introduced in the design. Other BIST design techniques attempt to avoid scan dependence because it can reduce the fault coverage of embedded, multiple input signature registers (MISRs). We show that introducing certain types of scan dependence in embedded MISRs can result in reduced overhead and improved fault coverage. We present our results for benchmark circuits that have been synthesized to take advantage of scan dependence in a circular BIST architecture.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Testing and diagnosis techniques play a key role during the advance of semiconductor memory technologies. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and yield improvement. The test and diagnosis complexity are 12N for bit-oriented diagnosis algorithm, N is the number of addresses is proposed for fault detection and diagnosis. Using the proposed march-based algorithm (march-12N), 100% of the faults under the fault model are covered and partial distinguished. They also can locate the faulty cells and identify their types. The complete fault and diagnosis procedures for state coupling faults, idempotent coupling faults and inversion coupling faults are written in this paper. Therefore, all the coupling faults that occur in SRAM memories are verified and proved the valid results. Furthermore, the realistic 12N test and diagnosis algorithm has shown the improvement of diagnostic resolution and test time.

The proposed work has a test pattern generator for built-in self-test (BIST) based applications along with test data compression. Test patterns are produced with desired levels of toggling and improved fault coverage is obtained when compared with BIST-based pseudorandom pattern generators (PRPG). The pattern generator comprises of a pseudorandom pattern generation unit, a toggle generation and control unit, a hold register unit. Preselected toggling (PRESTO) generator allows user defined levels of toggling. The pattern generator is a linear finite state machine which drives a phase shifter, which reduces correlation of patterns. This paper proposes a test compression method which elevates the compression efficiency that has not been obtained by conventional compression techniques. It does not need any core logic modifications like test point insertion and thus the compression technique is nonintrusive. This hybrid technique of BIST along with test compression achieves fault coverage above 90%. Experimental results are obtained for ISCAS 85, ISCAS 89 and ITC 99 standard benchmark circuits. The PRESTO generator can effectively function as a decompressor also and hence area is reduced.

The effectiveness of testing the analog part of mixed-signal circuits impacts their overall manufacturing cost. Therefore, it is important to have accurate metrics to estimate fault coverage and to precisely measure the test quality. In this paper, we propose an accurate testability analysis based on multi-frequency test pattern generation and a new testability measure called the parameter fault coverage (PFC) that takes into account the continuous characteristic of the parametric faults spectrum and masking effect of process variations. This new analog test metric allows accurately measuring analog test quality and enables taking better decisions regarding the use of design for testability (DFT) techniques. Therefore, poor product test quality and unnecessary design modifications, which may be caused by incorrect fault coverage estimates, can be avoided.

Background: patients with rifampicin-resistant tuberculosis (RR-TB; including multidrug-resistance with added isoniazid resistance) require longer and more complex treatment than those with drug-susceptible disease. The global response to RR-TB will influence progress towards the post-2015 targets of the End TB Strategy of the World Health Organization (WHO). Methods: aggregated surveillance data reported annually by Member States allow WHO to monitor key indicators of the global RR-TB response, namely coverage of susceptibility testing, case detection, enrolment on treatment, and treatment success. Findings: about 340,000 RR-TB cases were estimated to occur among the pulmonary TB patients notified worldwide in 2014. While coverage of testing for RR-TB reached 12% of new and 58% of previously-treated TB cases notified that year, only 36% (122,618 patients) of estimated RR-TB cases were reported worldwide. In 2014, 110,803 TB patients were known to have started second-line TB treatment. Only 50% of RR-TB cases starting treatment in 2012 completed it successfully. Testing for RR-TB and treatment enrolments increased steadily over time, but case detection and treatment success remained at the same levels. Interpretation: improvements in coverage of testing and treatment for RR-TB are a result of the widespread roll-out of molecular diagnostics (e.g. Xpert MTB/RIF) and better access to second-line TB medication respectively. These efforts need to be stepped up and matched by a better identification of patients at risk of drug-resistance to be tested, more efficient capture of surveillance data and enhanced access to more effective regimens and social support for patients on treatment.

The purpose of this paper is to introduce a new RTL testability metric, IFMB, that evaluates the exercise of Implicit Functionality (IF) of operators and Multiple Branch (AM) coverage of conditional constructs. Although physical Defect Coverage (DC) strongly depends on the logic structure, thus preventing accurate DC estimation, RTL fault models can be derived, targeting high correlation between RTL fault coverage and DC. Using this evaluation criterion, previous RTL coverage metrics are compared with new metric. Due to its excellent correlation to DC, IFMB allows, at RT-level, test pattern quality evaluation aiming its reuse as production or lifetime test, using BIST. A methodology for testability analysis with the proposed RTL fault models is also presented, based on fast fault simulation using random patterns. Simulation based testability analysis errors are quantified Examples are presented where the proposed testability metrics are used to guide the inclusion of BIST in modules of ITC'99 benchmark circuits.

Built-in self-test (BIST) is a key design-for-testability technique for digital systems in nanometre technologies. BIST design is usually quite intrusive. In fact, BIST-per-scan or BIST-per-clock schemes require the replacement of all circuit registers by modified flip-flops or registers with extra functionality, which may lead to unacceptable area overhead and, especially, performance degradation. However, for some applications, system performance cannot be compromised by BIST insertion. Moreover, many applications have multiple clock domains and need to be self-tested at speed, during product lifetime. The functional-oriented mask-based BIST is proposed as a minimum impact BIST design methodology. The proposed approach uses testability metrics and circuit functionality to iteratively obtain a BIST solution with the required fault coverage (FC). It can be implemented in multiple clock domain designs and lead to short BIST sessions and a limited impact on system performance. A real world case study, for which system performance is critical, is used to demonstrate that high FC values in a sequential circuit can be achieved, operating at-speed with multiple clock signals, with minimum performance degradation and with lower hardware overhead than the one obtained with a BIST-per-scan solution. The case study is a two-clock domain Sync core for the Synchronisation and Link Board of electromagnetic calorimeter and hadron calorimeter detectors of the CERN compact Muon solenoid experiment.