A Realistic March-12N Test And Diagnosis Algorithm For SRAM Memories

Efficient march test for 3-coupling faults in random access memories

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

This report describes models of building faults created for OpenStudio to support the ongoing development of fault detection and diagnostic (FDD) algorithms at the National Renewable Energy Laboratory. Building faults are operating abnormalities that degrade building performance, such as using more energy than normal operation, failing to maintain building temperatures according to the thermostat set points, etc. Models of building faults in OpenStudio can be used to estimate fault impacts on building performance and to develop and evaluate FDD algorithms. The aim of the project is to develop fault models of typical heating, ventilating and air conditioning (HVAC) equipment in the United States, and the fault models in this report are grouped as control faults, sensor faults, packaged and split air conditioner faults, water-cooled chiller faults, and other uncategorized faults. The control fault models simulate impacts of inappropriate thermostat control schemes such as an incorrect thermostat set point in unoccupied hours and manual changes of thermostat set point due to extreme outside temperature. Sensor fault models focus on the modeling of sensor biases including economizer relative humidity sensor bias, supply air temperature sensor bias, and water circuit temperature sensor bias. Packaged and split air conditioner fault models simulate refrigerant undercharging, condenser fouling, condenser fan motor efficiency degradation, non-condensable entrainment in refrigerant, and liquid line restriction. Other fault models that are uncategorized include duct fouling, excessive infiltration into the building, and blower and pump motor degradation.

F2G: A hybrid fault-function graphical model for reliability analysis of complex equipment with coupled faults

Proposes a new analog coupling delay fault model and analog macromodeling technique to generate tests for these faults. To our knowledge, this is the first time that analog macromodeling, along with multiple-delay sequential digital fault simulation, using differing rise and fall times for digital logic gates, effectively detected coupling timing faults. We propose a new crosstalk candidate reduction (CCR) algorithm, which looks at the entire set of possible signal line couplings and eliminates impossible and uninteresting couplings from the final list. On various circuits, CCR reduced the coupling candidates by 98.1%, on average. The analog macromodels eliminate errors and uncertainty about whether signals actually couple, and also avoid complete analog simulation during fault simulation, as all analog macromodels are precomputed. The analog macromodel is independent of the circuit-under-test, because it models generalized interconnect. The method efficiently handles large circuits with more than 10,000 coupling faults, while obtaining coupling fault coverages in the range of 4 to 10% on sequential circuits, and up to 33% on combinational circuits. These are the first coupling fault results for sequential circuits.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative technology for on-chip memories due to several advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Due to the emerging fabrication processes of magnetic layers in the fabrication of STTMRAM devices, they are more susceptible to manufacturing defects and have different failure mechanisms compared to conventional CMOS memories. This mandates specific fault modeling and development of proper test algorithms for high coverage testing of these memories in order to ensure correct functionality in the field. In this paper, a detailed defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults.

In the coupling state of rotor unbalance fault and bearing defect fault for rotor system, the signals contain multiple fault components, and the fault diagnosis of the rotor system needs to contain comprehensive multidimensional feature quantities. However, irrelevant feature information in the multi-dimensional feature quantities increases the complexity of classification calculation and affects the efficiency and accuracy of diagnosis. In order to eliminate redundant and irrelevant features in the feature information, and achieve the goal of fewer diagnostic features and good diagnostic results, this paper proposes an adaptive feature selection based on the maximum information coefficient FF-FC-MIC (Feature-to-Feature and Feature-to-Category Maximum Information Coefficient) method. Firstly, the sparse representation algorithm is used to reconstruct the original signal to improve the signal-to-noise ratio, and the multi-dimensional feature quantity of the reconstructed signal is calculated; Secondly, calculate the correlation between features and features through MIC to obtain a feature set of weak correlation between features; thirdly, use MIC to calculate the correlation between features and signal categories to obtain a feature set with strong correlation between features and signals; Finally, the FF-FC-MIC feature selection method is used for feature adaptive selection and input into SVM to complete fault diagnosis. The method is analyzed by simulation signals and the real experiment signals. The results show that the method can effectively remove redundant and disclosed features in the coupling fault, reducing the characteristic dimension to reduce the fault classification time, and improve classification accuracy. Different experimental cases and various feature selection comparison methods further verify the accuracy and applicability of the proposed method.

This paper presents a test synthesis technique for behavioral descriptions. The technique is guided by two testability metrics which quantify the controllability and observability of behavioral variables and structural signals. The method is based on utilizing redundant register transfers in the data path to produce a test behavior with better controllability and observability properties. This approach can avoid unnecessary insertions of test structures in the data path. A test scheme for conditional statements has been developed involving minimal changes in the controller. Our experimental results show improvements in fault coverage at modest hardware overhead.

Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are awake-mode stuck-at fault, sleep-mode stuck-at fault, awake-mode transition fault, and sleep-mode transition fault. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Based on the new fault models, test patterns for retention flip-flop can be easily generated by current automatic test pattern generation tools. The proposed test methodology is validated by performing experiments on ISCAS'89 benchmark circuits and some realistic industrial low power designs. The experimental results show that the faults of retention flip-flops can be easily detected by our method and the average fault coverage is higher than 98%. The fault coverage of conventional single stuck-at fault and transition fault test can be increased by more than 1%.

The authors propose design for testability at the logic synthesis level. Their state assignment is aimed at producing a reduced feedback or pipeline like structure which is easily analyzed by a sequential circuit test generator. State variables are assigned one at a time such that a state variable depends only on primary inputs and the previously assigned state variables. This results in a purely pipeline structure for finite-memory or definite machines. For other machines, the number of cycles in the implemented structure is minimized. The authors give several examples to compare their reduced feedback synthesis with another method that is aimed at reducing the amount of logic in a multilevel implementation. Results show a marked improvement in test generation time and fault coverage; in terms of logic their method did just as well as the other method. >

Fault Modeling, Testing, and Repair for Chiplet Interconnects

Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and the product cost of many SoCs. In order to provide an efficient testing method for 865–870 MHz Charge pump phase-locked loop (CP-PLL) which constitutes a mixed-signal circuit a novel BIST method is developed. This BIST can be easily implemented with a test stimulus generator circuit, all existing blocks in CP-PLL and fault evaluation circuit. In order to reduce the chip area overheard, this technique use a selection circuit and one delay cell. The simulation results of the novel technique show high fault coverage 100% like that of our previous testing methods. Thus, it provides an efficient structural test suitable for a production test in terms of an area overhead, a test accessibility, and test time.

This paper presents techniques to improve compressions by improving fault coverage that can be achieved by broadcast scan. Due to reconvergent gates that artificially occur in broadcast scan, broadcast scan fault coverage is often much lower than standard serial scan fault coverage. The proposed scan chain reordering technique improves broadcast scan fault coverage by minimizing the number of reconvergent gates and hence no or very small number of test patterns are required to be applied by standard serial scan to detect faults undetected by broadcast scan. This increases the overall compression ratio. To eliminate or minimize increase in routing overhead, the distance that each scan cell can be relocated by the scan chain reordering procedure is limited. Test points are inserted to further reduce correlation among outputs of scancells. The proposed scan chain reordering technique improved broadcast scan fault converge by up to 8.5%. Large fault coverage improvement was achieved by the proposed method, especially for circuits that suffer low broadcast scan fault coverage. Broadcast scan fault coverage for the largest two industrial designs was even higher than standard serial scan fault coverage.

Background: patients with rifampicin-resistant tuberculosis (RR-TB; including multidrug-resistance with added isoniazid resistance) require longer and more complex treatment than those with drug-susceptible disease. The global response to RR-TB will influence progress towards the post-2015 targets of the End TB Strategy of the World Health Organization (WHO). Methods: aggregated surveillance data reported annually by Member States allow WHO to monitor key indicators of the global RR-TB response, namely coverage of susceptibility testing, case detection, enrolment on treatment, and treatment success. Findings: about 340,000 RR-TB cases were estimated to occur among the pulmonary TB patients notified worldwide in 2014. While coverage of testing for RR-TB reached 12% of new and 58% of previously-treated TB cases notified that year, only 36% (122,618 patients) of estimated RR-TB cases were reported worldwide. In 2014, 110,803 TB patients were known to have started second-line TB treatment. Only 50% of RR-TB cases starting treatment in 2012 completed it successfully. Testing for RR-TB and treatment enrolments increased steadily over time, but case detection and treatment success remained at the same levels. Interpretation: improvements in coverage of testing and treatment for RR-TB are a result of the widespread roll-out of molecular diagnostics (e.g. Xpert MTB/RIF) and better access to second-line TB medication respectively. These efforts need to be stepped up and matched by a better identification of patients at risk of drug-resistance to be tested, more efficient capture of surveillance data and enhanced access to more effective regimens and social support for patients on treatment.

A parameterized graph-based framework for high-level test synthesis