A real-time H.264 MP decoder based on a DM642 DSP

The H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In order to accelerate the decoding speed, several algorithmic optimisations have been ported to inverse entropy decoding and intra-prediction modules. The parallelism between algorithm execution and data transfers was fully exploited using Enhanced Direct Memory Access (EDMA) engine. Furthermore, based on the DSP architectural features, various core-specific optimisation techniques were adopted leading to an increase in speed by up to 70%. Intensive experimental tests prove that a real-time decoding on TMS320C6416 DSP running at 720 MHz is obtained for Common Intermediate Format resolution (CIF 352 × 288)

Data warehouse store historical records on which analysis queries are executed. Data warehouse are populated from the transaction database through a process called as Extract Transform and Load (ETL). Extract is to identify the transaction database records to be moved to the data warehouse. Transform is to make the records normalized to suit the data warehouse environment. Load is to actually store the records in the data warehouse. Today business wants to perform real time analysis of data. Availability of updated records in the data warehouse is necessary for real time analysis. This could be achieved through the process of near real time (ETL), i.e., to improve existing ETL process. Improvement to existing ETL could be achieved in many ways such as to increase the frequency of loads, to identify relevant changes that are required for analysis and move only those changes. Only through increasing the frequency of load would not be useful in many cases. Hence we should identify the changes and then move if they are useful for analysis making it smart ETL. In this paper we study three such techniques. First one is to create a replica of dimension table in data warehouse and move the changes to the replica this reduces the query response time. Second is to load the data in parallel so that loading time could be reduced. Third is to identify changes and trigger the loading process. We have used the first approach to create replica and loaded the data in parallel and observed that by loading in parallel not only does the loading time reduces but also the query response time. Then in the first approach is the query response time reduces to a certain limit methods suggest to move the data from replica dimensions to the original dimensions. Here we bring in right time trigger to move instead of just the query response time. We found that when we have a combined approach to query response time and right time trigger the number of moves are reduced.

Real time analysis has become a norm in today's fast and competitive business environment. Availability of recent data is a requirement to perform real time analysis. The data warehouse is meant to store historical data for analysis and these are populated from time to time through a process called as extract transform and load (ETL). The ETL process was done during nights or weekends to make the transactional data available at the data warehouse for analysis. But the delay of a day or weekend is not acceptable for real time analysis hence a concept of near real time ETL is developed to perform real time analysis. We explore in this study methods of how near real time ETL could be achieved. We focus on three ways of how near real time ETL could be performed. First is the Meta data management which if done effectively will greatly reduce the development time. Second is the concept of change data capture when implemented with some intelligent would greatly help in making the correct data available for analysis at the warehouse. The third is the use of parallel techniques to partition the flow of ETL and reduce the time window with which the data are available at the warehouse.

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

Data-intensive applications such as image processing suffer from massive data movement between memory and processing units. The severe limitations on system performance and energy efficiency imposed by this data movement are further exacerbated with any increase in the distance the data must travel. This data transfer and its associated obstacles could be eliminated by the use of emerging non-volatile resistive memory technologies (memristors) that make it possible to both store and process data within the same memory cells. In this paper, we propose four in-memory algorithms for efficient execution of fixed point multiplication using MAGIC gates. These algorithms achieve much better latency and throughput than a previous work and significantly reduce the area cost. They can thus be feasibly implemented inside the size-limited memory arrays. We use these fixed point multiplication algorithms to efficiently perform more complex in-memory operations such as image convolution and further show how to partition large images to multiple memory arrays so as to maximize the parallelism. All the proposed algorithms are evaluated and verified using a cycle-accurate and functional simulator. Our algorithms provide on average $200\times $ better performance over state-of-the-art APIM, a processing in-memory architecture for data intensive applications.

SummarySeveral important tasks, including matrix computation, signal processing, sorting, dynamic programming, encryption, and decryption, can be performed by oblivious sequential algorithms. A sequential algorithm is oblivious if an address accessed at each time does not depend on the input data. A bulk execution of a sequential algorithm is to execute it for many independent inputs in turn or in parallel. A number of works have been devoted to design and implement parallel algorithms for a single input. However, none of these works evaluated the bulk execution performance of these algorithms. The first contribution of this paper is to present a time‐optimal implementation for bulk execution of an oblivious sequential algorithm. Our second contribution is to develop a tool, named C2CU, which automatically generates a CUDA C program for a bulk execution of an oblivious sequential algorithm. The C2CU has been used to generate CUDA C programs for the bulk execution of the bitonic sorting, Floyd‐Warshall, and Montgomery modulo multiplication algorithms. Compared to a sequential implementation on a single CPU, the generated CUDA C programs for the above algorithms run, respectively, 199, 54, and 78 times faster.

Real-time analysis of data is the new trend to get useful insights in very less time spend on data preprocessing. Analysis of data requires the movement of data from various heterogeneous/homogenous sources to a common place known as the data warehouse. Data source for data warehouse is the transaction processing systems. Movement of data from the transactional database to the data warehouse is done using the process of extract, transform, and load (ETL). ETL previously was done during of peak hours like a night load or on weekends. The requirement of real-time analysis demands the ETL to be fast and not wait for off-peak hours. This leads to the concept of near real-time ETL, and here techniques are employed to identify the potential changed data at the transaction database and move it to the analysis database with a very minimal delay. This movement of data in real time from multiple sources in an incremental form could lead to anomalies in the data warehouse. This work discusses the various causes of anomalies and solutions to overcome them. Our main contribution is the application of loading data into temporary tables for reducing query execution time in case of overcoming refreshment anomalies.

The development of floating point digital signal processors (DSP) has led to a significant improvement in digital signal processing. This paper presents the application of a floating point DSP to the real time data processing and control of a dynamic robot measurement system, which is based on a single laser beam that is deflected over a mirror mounted to a beam steering mechanism. The specifications with regard to high accuracy of the measurement system and the cycle time for the numerous calculations that are performed to acquire the desired measurement data are reached with dedicated data acquisition modules that are connected via a 32 bits bus to a DSP. This configuration allows measurements with more than 10 kHz sampling rare and the execution of a sophisticated prediction control algorithm at the same rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Our research concentrates on developing a novel HDTV content management system that enables end users to search, retrieve and browse archived standard definition (SD) and high definition (HD) television material for program production and content repurposing in a digital television studio. We have developed the first system that automatically analyzes motion occurring in MPEG-2 coded SD and HD videos within the compressed domain itself and produces descriptors characterizing the global visual motion in videos, for content-based search and retrieval applications. We describe our robust and efficient scheme for automatically generating a flow characterization of a video bitstream without decompression, which is a frame-type-independent uniform motion representation amenable for consistent interpretation and computed from the raw motion vectors encoded in the MPEG-2 bitstreams. We propose novel techniques to handle all the different prediction schemes that are employed with different frame types and picture structures of MPEG-2 during the motion compensation process to deal with interlaced and progressive modes. Experiments with thousands of frames from SD and HD video streams demonstrate the accuracy of our flow estimation process and the effectiveness of utilizing flow vectors for annotation of perceived global motion in video streams.

A revision of IEEE Std 1641 is coming to an end and is undergoing its approval cycle. This standard, which provides a method of accurately defining signals and tests, has been further developed with many improvements. The use of signals and events has now been extended to include digital signals. These three elements, physical signal streams, event streams and digital streams, provide the vital backbone to the description of all signals, simple or complex. They define when a signal may exist and when it may not, when a signal has a value and when it has not, when it starts and when it stops. Understanding the operation of SignalFunctions of different types and the operation of the signal, event and digital streams is essential to the building of Test Signal Framework (TSF) models, especially those which include complex timing relationships. This paper explains each of these streams and how they interact one with another.

Context. The digital signal processing is applied in many fields of science, technology and human activity. One of the ways of implementing algorithms of digital signal processing is the development of coprocessors as an integral part of well-known architectures.&#x0D; In the case of developing a pipelined device, the presented approach will allow to use software and hardware tools of the appropriate architecture, provide the faster execution of signal processing algorithms, reduce the number of cycles and memory accesses.&#x0D; Objective. Objectives are design and characterization study of a pipelined RISC-V processor and coprocessor of digital signal processing which performs fast Fourier transform.&#x0D; Method. Analyzing technical literature and existing decisions allow to assess advantages and disadvantages of modern developments and on the basis of which to form the relevance of the selected topic. Model designing and simulation results allow to examine a model efficiency, to determine weak components’ parts and to improve model parameters.&#x0D; Results. The pipelined RISC-V processor has been designed which executes a basic set of instructions. Execution time of assembly program on the single-cycled and the pipelined processors have been analyzed. According to the results, the test program on the pipelined processor is executed in 29 cycles, while on the single-cycle processor it takes 60 cycles. The structure of the coprocessor for the fast Fourier transform algorithm and a set of processor instructions that allow working with the coprocessor have been developed. The number of cycles of the coprocessor based on Radix-2 fast Fourier transform algorithm for 512 points is 2358 cycles, and for 1024 points is 5180 cycles.&#x0D; Conclusions. Conducted researches and calculations have showed that the application of the developed hardware coprocessor reduces the fast Fourier transform algorithm execution time and the load of the pipelined processor during calculations.

The authors present the use of the multimesh graph representation to map matrix algorithms onto arrays of digital signal processors (DSPs), using the TMS 320C30 as example. This processor, as most DSPs, is characterized by a two-level memory subsystem and a built-in DMA controller. The mapping process focuses on large matrices which do not fit in the first level of memory. Good utilization of the DSP resources is achieved by programming the execution of the algorithms by prisms from the multimesh graph; the optimal size of the prisms is obtained. Performance estimates indicate that it is possible to program the DSP in such a way that the impact of slower second-level memory is not significant (around 7% degradation with five wait states). Good load balancing throughout the array is achieved by allocating to processors partitions of the problem of nonuniform size, as suggested in a previous publication. The schedule of operations proposed deviates from the conventional ordering, wherein the inner-product among two vectors is fully computed at once. Instead, the proposed schedule divides inner-products into portions which are executed in interleaved manner throughout the computation of the entire problem, each portion using as an input the partial result obtained earlier from the execution of the corresponding previous portion. >

In order to fulfil real time signal processing tasks such as clutter rejection, moving target detection (MTD) and constant false alarm rate (CFAR) control in airborne radar, an airborne radar parallel signal processing system (ARPS2) is proposed with DSP chips as its kernel processing nodes. The DSP chips are used with parallel architecture. Each node has its private input and output memory. It adopts several parallel techniques, such as parallel storage, parallel processing, parallel code loading and parallel data organization to achieve high efficiency. It has a simple structure, excellent flexibility and easiness in developing. ARPS2 is going to be applied to an airborne radar. It can also be applied to perform high-speed real time signal processing algorithms in other kinds of radar.

Big Data is an emerged architecture and technology paradigm that is used by many organizations to extract valuable information either to take decisions. Big Data is a technique and method used to retrieve, collect, process and analyze a very big volume of unstructured and structured data. The challenge is processing and analyzing the huge volume of data coming in from network sensors. Practically, it’s too late to stop an abnormal comportment, if we collect the incoming streams and wait for many days for processing and analyzing the stored streams. Big Data in video surveillance systems, offer ETL (Extract Transform and Load) challenges related to the Van Newman Bottleneck and Data Locality. In this chapter we propose a conceptual model with architectural elements and proposed tools for monitoring in RTAP (Real Time Analytical Processing) mode smart areas.

Objective. Surface electromyography (EMG) decomposition techniques can be used to establish human-machine interfacing (HMI), but most investigations are implemented offline due to the computational load of the approach. Here, we generalize the offline decomposition algorithm to identify the motor unit (MU) activities in real time, and we propose a MU-based approach for online simultaneous and proportional control (SPC) of multiple motor tasks. Approach. High-density surface EMG signals recorded from forearm muscles were decomposed into motor unit spike trains (MUSTs) with the proposed decomposition method. The MUSTs were first pooled into clusters in the calibration phase and the cumulative discharges of active MUs in each group were extracted as the control signal for each motor task. Then the subjects were instructed to control a virtual cursor with multiple motor tasks involving grasp and wrist movements. Fifteen able-bodied subjects and two patients with limb deficiency participated in the experiments to validate the proposed control scheme. Main results. On average, over 20 MUSTs were identified in real time with an estimated decomposition accuracy > 85%. The cumulative discharge in each pool was highly correlated with the activation of the specific motion (R = 0.93 ± 0.05). Moreover, the proposed MU-based method had superior performance in online tests than conventional myo-control methods based on global EMG features. Significance. These results indicate the feasibility of real-time neural decoding in a non-invasive way. Moreover, the superior performance in online tests proves the potential of the MU-based approach for the SPC, promoting the application of EMG decomposition for HMI systems.