A single-chip MPEG-2 codec based on customizable media embedded processor

Improving System Predictability and Performance via Hardware Accelerated Data Structures

Application-specific instruction set extension is an effective technique for reducing accesses to components such as on- and off-chip memories, register file and enhancing the energy efficiency. However, the addition of custom functional units to the base processor is required for supporting custom instructions, which due to the increase of manufacturing and design costs in new nanometer-scale technologies and shorter time-to-market, is becoming an issue. To address above issues, in our proposed approach, an optimized reconfigurable functional unit is used instead, and instruction set customization is done after chip-fabrication. Therefore, while maintaining the flexibility of a conventional microprocessor, the low-energy feature of customization is applicable. Experimental results show that the maximum and average energy savings are 67% and 22%, respectively for our proposed architecture framework.

Application-specific instruction-set processors (ASIPs) allow the designer to extend the instruction set of the base processor with selected custom instructions to tailor-fit the application. In this paper, with the help of a motivational example, we first demonstrate that different custom instructions are vulnerable to faults with varying probabilities. This shows that by ignoring the vulnerability to faults, traditional methods of instruction set customization can provide no guarantees on the reliability of the system. Apart from such inherent disparity in error vulnerability across custom instructions, each custom instruction can have multiple implementation choices corresponding to varying hardened levels. Hardening reduces the vulnerability to errors but this comes at the overhead of area costs and reduced performance gain. In this paper, we propose a framework to select custom instructions and their respective hardening levels such that reliability is optimized while the performance gain is satisfied and area costs are met as well. Our framework is based on a novel analytical method to compute the overall system reliability based on the probability of failure of individual instructions. Wide range of experiments that were conducted illustrate how our tool navigates the design space to reveal interesting tradeoffs.

In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instructions that can be implemented in special hardware units make it possible to improve performance and decrease power consumption in extensible processors. The key issue involved is to generate and select automatically custom instructions from a high-level application code. In this paper, we propose an efficient and flexible algorithm for the exact enumeration of custom instructions. The algorithm can be tuned to generate all possible patterns or only connected patterns. Compared to a previously proposed well-known algorithm, our algorithm can achieve orders of magnitude speedup.

Objective. Surface electromyography (EMG) decomposition techniques can be used to establish human-machine interfacing (HMI), but most investigations are implemented offline due to the computational load of the approach. Here, we generalize the offline decomposition algorithm to identify the motor unit (MU) activities in real time, and we propose a MU-based approach for online simultaneous and proportional control (SPC) of multiple motor tasks. Approach. High-density surface EMG signals recorded from forearm muscles were decomposed into motor unit spike trains (MUSTs) with the proposed decomposition method. The MUSTs were first pooled into clusters in the calibration phase and the cumulative discharges of active MUs in each group were extracted as the control signal for each motor task. Then the subjects were instructed to control a virtual cursor with multiple motor tasks involving grasp and wrist movements. Fifteen able-bodied subjects and two patients with limb deficiency participated in the experiments to validate the proposed control scheme. Main results. On average, over 20 MUSTs were identified in real time with an estimated decomposition accuracy > 85%. The cumulative discharge in each pool was highly correlated with the activation of the specific motion (R = 0.93 ± 0.05). Moreover, the proposed MU-based method had superior performance in online tests than conventional myo-control methods based on global EMG features. Significance. These results indicate the feasibility of real-time neural decoding in a non-invasive way. Moreover, the superior performance in online tests proves the potential of the MU-based approach for the SPC, promoting the application of EMG decomposition for HMI systems.

This chapter presents the novel adaptive low-power reconfigurable processor architecture with a run-time adaptive energy management scheme. It exploits the novel concept of Selective Instruction Set Muting with multiple muting modes. The first section analyzes different scenarios, while motivating the need for run-time energy management. Afterwards, the adaptive energy management scheme with the novel concept of Custom Instruction (CI) Set Muting is discussed in Sect. 5.2. In this section different CI muting modes are explained along with the corresponding configuration of sleep transistors for different parts of the reconfigurable fabric. Afterwards, the required power-shutdown infrastructure is discussed. In Sect. 5.2.3 an overview of the energy management scheme is provided highlighting different requirements and steps considered at design-, compile-, and run-time.

The H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In order to accelerate the decoding speed, several algorithmic optimisations have been ported to inverse entropy decoding and intra-prediction modules. The parallelism between algorithm execution and data transfers was fully exploited using Enhanced Direct Memory Access (EDMA) engine. Furthermore, based on the DSP architectural features, various core-specific optimisation techniques were adopted leading to an increase in speed by up to 70%. Intensive experimental tests prove that a real-time decoding on TMS320C6416 DSP running at 720 MHz is obtained for Common Intermediate Format resolution (CIF 352 × 288)

In this paper, the implementation of a Main Profile H.264 decoder based on a DM642 digital signal processor is described. An initial standard compliant raw-C decoder has been optimized in speed for the target processor. The parallelism between algorithm execution and data movement has been fully exploited using DMA. Also, critical parts of the algorithm have been encoded directly in assembly code to increase the number of instructions per cycle. The decoder has been tested in simulation with actual (transcoded) DVD and digital TV streams. According to these tests, standard definition (Dl) real time decoding can be obtained with a DM642@720 MHz.

Heterogeneous-ISA multi-core architectures have emerged as a promising design paradigm given the ever-increasing demands on single threaded performance. Such architectures comprise multiple cores that differ not just in micro-architectural parameters (e.g., fetch width, ROB size) but also in their Instruction Set Architectures (ISAs). These architectures extract previously latent performance gains by executing different phases of the program on the core (and ISA) best suited to it, as opposed to executing the entire program on a single ISA. In such a computing paradigm, maximum performance is only extracted when we ensure that at every point in the program’s execution, the program runs on the core best suited to it. In this work, we propose a migration framework that practically and accurately decides when to migrate the program across different cores (and ISAs) to extract maximum performance gains. Under the covers, this framework combines a regression based performance modelling technique with a greedy scheduling algorithm. Our performance modelling technique leverages hardware performance counters prevalent in all major processors today to accurately estimate the performance of the program on different ISAs to within an error of 6%. Putting it together with our greedy scheduler enables our framework to achieve single thread performance speedups of 29.6% with respect to a baseline single ISA heterogeneous architecture.

Recent research has shown that field programmable gate arrays (FPGAs) have a large potential for accelerating demanding applications, such as high performance digital signal process applications with low-volume market. The loss of generality in the architecture is one disadvantage of using FPGAs, however, the reconfigurability of FPGAs allow reprogramming for other applications. Therefore, a uniform FPGA-based architecture, an efficient programming model, and a simple mapping method are paramount for the wide acceptance of FPGA technology. This paper presents MASALA, a dynamically reconfigurable FPGA-based accelerator for parallel programs written in thread-intensive and explicit memory management (TEMM) programming models. Our system uses a TEMM programming model to parallelize demanding applications, including application decomposition into separate thread blocks and compute and data load/store decoupling. Hardware engines are included into MASALA using partial dynamic reconfiguration modules, each of which encapsulates a thread process engine that implements the hardware's thread functionality. A data dispatching scheme is also included in MASALA to enable the explicit communication of multiple memory hierarchies such as interhardware engines, host processors, and hardware engines. Finally, this paper illustrates a multi-FPGA prototype system of the presented architecture: MASALA-SX. A large synthetic aperture radar image formatting experiment shows that MASALA's architecture facilitates the construction of a TEMM program accelerator by providing greater performance and less power consumption than current CPU platforms, without sacrificing programmability, flexibility, and scalability.

The application specific instruction-set processor (ASIP) offers better computing performance and efficiency by exploiting a set of specific custom instructions (CI) in the processor. However, traditional approaches suffer from the problem that it costs so much computational resource to enumerate and select the optimal custom instructions. In this paper, instead of generating the custom instructions by enumerating all sub-graphs in the data flow graph, we propose a novel custom instruction generation algorithm based on analyzing the basic blocks (BB) which are the smallest execution units of the program. On the basis of characterizing the logic information and structure of basic blocks, both the identification and selection processes could be more efficient by focusing on the feasible candidates with better benefits. A Maximal Weight Independent Set-based formulation is set up to select the final custom instructions based on the efficient identification of candidate custom instructions with logic information of BBs. The experimental result shows that our algorithm can identify 55% more feasible CIs compared with the previous approach. With efficient identification process, we can finally get better CI designs with about 3.27X performance gain of the whole system.

Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

IBM had four incompatible computer lines. Each had its own unique instruction-set architecture (ISA); I/O system; system software (assemblers, compilers, libraries); and market niches (business, scientific, real time). IBM engineers bet that they could invent a single ISA that would work for customers of all four lines. Moreover, the same program would run correctly on any implementation of that ISA, though at different speed and cost. That vision required a new way to build computers that would be binary compatible from the cheapest 8-bit model to the fastest 64-bit version.

Welcome to the 2012 Conference on Compilers, Architectures and Synthesis for Embedded Systems -- CASES'12! We are very pleased to continue the CASES tradition of bringing a unique focus on the intersection of compilers and architectures to Embedded Systems Week (ESWEEK). CASES has served this purpose since 2006 when it first formed part of the three core conferences that comprise ESWEEK. This year, the program emphasizes a number of trends in compilation technology, architectures and memory systems. Some highlights include the keynote presentation from Professor Satnam Singh who explores the programming challenges we face as the well-established concept of the instruction set architecture (ISA) erodes with the emergence of heterogeneous architectures. Two invited papers further this dialogue by exploring new roles compilers and auto-tuners serve in the context of increasingly parallel and heterogeneous architectures. Several of the other sessions address old and new challenges in the context of memory systems. Among the latter is an especially important emphasis on security in memory. As the number of embedded systems per person shows no signs of slowing its dramatic increase over the past ten years, many predict that, in the next ten years, security will become as critical of an issue as energy consumption and power have come to be. It is for this reason we decided to open the conference with an invited paper on this topic. The CASES program committee accepted 18 out of 60 papers. All submissions received at least four reviews and half received five reviews. Every paper was discussed online, and the committee reached a number of decisions using online dialogue. This process allowed the committee to focus on a small number of papers at the face-to-face meeting where the program was finalized. This meeting was collocated with the Design Automation Conference (DAC) and held on June 3 in San Francisco, CA. The program this year consists of eight sessions and will follow a format established last year where each two-hour session has three papers and a final half-hour poster session. The poster session worked well in the past and we believe it affords a closer interaction between the authors and the attendees. We encourage you to take advantage of this format to have all of your questions answered! CASES is excited to be in Tampere, Finland -- home to Nokia, one of the largest producers of mobile phone technology. Finland also serves as an important link between Europe and Russia. It is exciting to have an opportunity to learn more about Finnish culture and technology. Several keynote speakers, a packed industrial session, and an excellent technical program will provide significant insight into the state of the art in embedded systems and the emerging challenges ahead. Finally, we would like to thank the many volunteers -- especially the CASES program committee and the ESWEEK local arrangements chairs, whose kind and dedicated effort make the conference possible.

Today, DAW (Digital Audio Workstation) software lies at the heart of music production and has become an indispensable part of the industry. With the advancement of technology, music production is no longer confined to large studios but has also become accessible to individual users. Now, recording, mixing, and mastering processes can be carried out in a home environment using computer-based systems, without the need for expensive equipment. This fully digital workflow is referred to as "in-the-box" production. Technological developments have enabled individuals to produce music at a professional level in home studios, leading to the emergence of digital alternatives to analog devices. Digital processors have begun to replace analog equipment due to their cost-effectiveness and practicality. This study examines the differences between digital signal processors and analog devices in terms of usage, application areas, and sound processing methods. The research aims to compare digital and analog signal processors, particularly focusing on their processing methods, speed, flexibility, quality, and impact on sound. Based on the findings, it is concluded that digital signal processors, which are increasingly replacing analog processors in the music industry, do not possess the same characteristics as their analog counterparts.