Real-time H.264/AVC baseline decoder implementation on TMS320C6416

Processing of the multiple data streams demand highperformance multiple transfers overburden the Processor System on Chips (SoC) in real time multimedia processing applications. High performance direct memory access (DMA) controller eases the processor as it performs bulk data transfer without the intervention of processor. This is true even in most artificial intelligence (AI) based systems and interleaving functions in communication systems where high-speed bulk data transfers are required. This is achieved by the design of Enhanced Direct Memory Access (EDMA) Controller, for high speed bulk data transfers. Paper presents the design of enhanced DMA core which is synthesizable ready to integrate for high performance AI based Digital Signal Processing SoC. The EDMA core is used for flexible Memory Access and bulk data transfers. EDMA core support several methods for data transfer between an input or output (I/O) device and the core processing unit. The processor in the SoC is used to program the Direct Memory Access (DMA) transfer instructions and actual transfers are performed by the EDMA core without the interference of processor. The EDMA design supports flexible addressing modes like linear, circular, step for bulk data transfers. The EDMA core is planned to be verified with test cases as in realistic application scenarios of interleaving, real time video processing.

In this work we present the analysis and implementation in a digital signal processor (DSP), of a variant of the Least Mean Square (LMS) algorithm. Modification is based on codifying the error of the algorithm, in order to reduce the design complexity for its implementation in digital adaptive filters, because the error is made up of whole values. The results demonstrate an increase in the convergence speed; it's affected indirectly by the convergence factor, and to obtain a floating point operation reduction, which accelerates processing. These, to demonstrate the results obtained from the implementation of the algorithm in the digital signal processor TMS320C6713 by Texas Instruments.

An instrument that accurately measures the profile of a surface in a real-time environment is proposed. The theoretical basis of the device is presented, with an explanation of how, through the analysis of fringe patterns using the fast Fourier transform, geometric parameters of a surface can be obtained. Hardware requirements for the proposed device are discussed, showing how the processing power and short cycle time of the TMS 320C25 digital signal processor (DSP) are used. The range of applications of this type of instrument is considered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The implementation of a digital sine wave oscillator using the TMS320C25 digital signal processor (DSP) is described. The system is implemented with the Dalanco Spry model 25 DSP board, and a software system is designed whereby an IBM PC host computer provides control of the waveform generator functions and parameters. Waveforms are generated using the lookup-table (LUT) method. The methods of direct LUT and linear interpolation of missing samples are implemented and compared with a method that uses a trigonometric identity to reduce the harmonic distortion of the sine wave by effectively increasing the table length of the direct LUT method. The results of an experiment performed in the digital domain are presented without consideration of the problem of analog reconstruction. The oscillator can produce a sine wave without the nonuniform sampling distortion associated with fractional addressing, over the range of 7.2 Hz to 58.8 kHz, with a resolution of 7.2 Hz using 384 data words. The trigonometric identity method uses less data memory than other methods for the same distortion levels. Waveforms for the sum of two sine waves, a frequency swept sine wave, amplitude modulation (AM), and frequency modulation (FM) signals are shown as applications of the waveform generator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

TMS320DM642(DM642) is a widely used digital media DSP chip. As with no Universal Asynchronous Receiver/Transmitter(UART) provided, it is difficult to communicate with other UART devices,especially in wireless video surveillance system.This paper uses on-chip multichannel buffered serial port(McBSP) and enhanced direct memory access(EDMA) to implement UART function based on DM642 and wireless communication module LC6311. The initialization of the McBSP and the data coding/decoding inprocess of transmitting/receiving are discussed in detail.This method can implement the communication between DM642 and LC6311 with easy program flow and no other devices. It enriches interface function of the DM642 and provides a new interface design for wireless video monitoring system.

The Texas Instruments (TI) C6678 “Shannon” is TI's most recently-released Digital Signal Processor (DSP). Although its original purpose was voice and video encoding and decoding, it may have the potential to become a practical coprocessor for scientific computing. In this paper, we evaluate the C6678 in terms of its programming methodology, performance, and power efficiency. As a case study, we implemented a sparse matrix vector multiply (SpMV) kernel and used it to perform a comparative study against the NVIDIA Kepler GK104 and GK106 Graphical Processor Units. On the DSP, we take advantage of many of the C6678's features, including its VLIW and SIMD instruction set architecture, program-controlled scratchpad memory, and direct memory access (DMA) controller. We found that the DSP is unable to outperform the GPUs in raw performance but can achieve roughly equal power efficiency in Gflops/Watt. This is more impressive when considering that the DSP is manufactured in a 45 nm process while the GPUs are manufactured in a 28 nm process. We believe that subsequent DSPs, when manufactured in a modern fabrication process, may be more competitive with GPUs in power efficiency. We also found that, for this kernel, the DSP is able to achieve higher utilization of both its peak memory bandwidth and its functional units as compared with the GPUs. In this paper we describe our kernel and the programming techniques required to optimize its performance.

A computationally efficient memory mapping predistorter is proposed to compensate for nonlinear distortion with memory induced by a combination of a linear pulse shaping filter and a travelling wave tube amplifier in orthogonal frequency division multiplexing (OFDM) systems. The proposed scheme utilizes a look up table (LUT) to store a small number of pre-calculated input-output relationships of the predistorter based on the fixed point iteration (FPI) we have presented in other study, and a simple memory mapping is employed for the data during actual system operation. We have implemented a 16-QAM, 256-subcarrier baseband OFDM modem and the proposed predistorter on a Texas Instruments' TMS320C30 digital signal processor, and experimental results show that the proposed predistorter achieves a very close performance of that based on the FPI even with a small LUT, while drastically reducing the computational complexity.

In this paper, a method for a parallel pipelined implementation of baseline JPEG compression and decompression is introduced for use on 4 Texas Instruments' TMS320C40 digital signal processors. A PC host with 2 Sonitech dual 'C40 boards is used for this implementation. The DCT is implemented using 2 'C40s, while quantization and Huffman encoding are each performed using a single 'C40. This novel implementation provides significant speedup over a sequential implementation by pipelining 8/spl times/8 blocks, through the parallel implementation.

The speed control of a SRM (switched reluctance motor) needs the accurate position and speed data of the rotor. This information is provided by a shaft encoder or a resolver. In some cases, high temperature, dust, and EMI may cause difficulties in maintaining the satisfactory position detection performance. The elimination of the position and speed sensor has gained wide attention. In this paper a new algorithm for the estimation of the rotor position and speed is proposed for the SRM drives. A nonlinear adaptive observer on the basis of the adaptive control theory is used to estimate the rotor speed and position. The stability of the adaptive observer is proved by the Lyapunov stability theorem. The adaptive observer estimates the rotor speed and position using the phase current and the estimated current. This algorithm was implemented with a DSP (digital signal processor) TMS320C31. Experimental results prove that the observer is able to estimate the speed and position.

The development of floating point digital signal processors (DSP) has led to a significant improvement in digital signal processing. This paper presents the application of a floating point DSP to the real time data processing and control of a dynamic robot measurement system, which is based on a single laser beam that is deflected over a mirror mounted to a beam steering mechanism. The specifications with regard to high accuracy of the measurement system and the cycle time for the numerous calculations that are performed to acquire the desired measurement data are reached with dedicated data acquisition modules that are connected via a 32 bits bus to a DSP. This configuration allows measurements with more than 10 kHz sampling rare and the execution of a sophisticated prediction control algorithm at the same rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The authors present the use of the multimesh graph representation to map matrix algorithms onto arrays of digital signal processors (DSPs), using the TMS 320C30 as example. This processor, as most DSPs, is characterized by a two-level memory subsystem and a built-in DMA controller. The mapping process focuses on large matrices which do not fit in the first level of memory. Good utilization of the DSP resources is achieved by programming the execution of the algorithms by prisms from the multimesh graph; the optimal size of the prisms is obtained. Performance estimates indicate that it is possible to program the DSP in such a way that the impact of slower second-level memory is not significant (around 7% degradation with five wait states). Good load balancing throughout the array is achieved by allocating to processors partitions of the problem of nonuniform size, as suggested in a previous publication. The schedule of operations proposed deviates from the conventional ordering, wherein the inner-product among two vectors is fully computed at once. Instead, the proposed schedule divides inner-products into portions which are executed in interleaved manner throughout the computation of the entire problem, each portion using as an input the partial result obtained earlier from the execution of the corresponding previous portion. >

Through the analysis of a data-flow-graph representation of an algorithm, the recent work by P.W. Lee (Ph.D. dissertation, Rutgers Univ., NJ, 1988) produces static, nonpreemptive schedules capable of implementing the algorithm on a multiple-processor system. These schedules are based on the assumptions that algorithms of the type that are typical of a class of digital signal processing (DSP) algorithms are computation bound (as opposed to I/O bound) and that data transfer (I/O operations) occurs instantaneously. This raises the question of the effects on the efficiency of the multiprocessor's utilization as the execution of the algorithm changes from computation bound to I/O bound. In the present work the author examines these effects for two cases of an algorithm (typical of this class of DSP algorithms). These cases are with and without a dominant run-time task, where a dominant run-time task is characterized by a far larger execution time than any other task in the algorithm. It is concluded that the ideal I/O assumption put forth by Lee is valid for software structures that exhibit dominant tasks. >

In next generation video surveillance systems there is a trend towards embedded solutions. Digital signal processors (DSP) are often used to provide the necessary computing power. The limited resources impose significant challenges for software development. Resource constraints must be met while facing increasing application complexity and pressing time-to-market demands. Recent advances in synthesis tools for Simulink suggest a high-level approach to algorithm implementation for embedded DSP systems. The model-based visual development process of Simulink facilitates simulation as well as synthesis of target specific code. In this work the modeling and code generation capabilities of Simulink are evaluated with respect to video analysis algorithms. Different models of a motion detection algorithm are used to synthesize code. The generated code targeted at a Texas Instruments TMS320C6416 DSP is compared to a hand-optimized reference. Experiments show that an ad hoc approach to synthesize complex image processing algorithms hardly yields optimal code for DSPs. However, several optimizations can be applied to improve performance.

A large and growing number of digital signal processor (DSP) applications are initially prototyped in Matlab, a high-level language that provides concise, intuitive statement of mathematical computations. Work in this elegant language stops at the prototyping stage due to the absence of an effective automatic path to implementation. This articles overviews a set of techniques for automating an implementation path from Matlab to DSPs and provides preliminary results on the effectiveness of such techniques.

In this paper, the implementation of a Main Profile H.264 decoder based on a DM642 digital signal processor is described. An initial standard compliant raw-C decoder has been optimized in speed for the target processor. The parallelism between algorithm execution and data movement has been fully exploited using DMA. Also, critical parts of the algorithm have been encoded directly in assembly code to increase the number of instructions per cycle. The decoder has been tested in simulation with actual (transcoded) DVD and digital TV streams. According to these tests, standard definition (Dl) real time decoding can be obtained with a DM642@720 MHz.