AN EVALUATION OF MODEL-BASED SOFTWARE SYNTHESIS FROM SIMULINK MODELS FOR EMBEDDED VIDEO APPLICATIONS

The 2022 International Conference on Image Processing and Intelligent Information Systems (IPIIS 2022) was successfully held online during October 22-23, 2022 in Zhengzhou, China. In the context of the conference, scholars and experts in the fields of image processing and intelligent information systems, involved both in experimental and theoretical research, were invited from various universities and institutions. The conference focused on the most recent advancements in topics such as 'Wireless Sensor Networks', 'Digital Signal Processing', 'Embedded Systems' and others.
 The main goal of IPIIS 2022 was to present the related research work, to promote the cooperation of experts and scholars in these fields, to share the research achievements both on a national and international level. This collection of proceedings compiles oral and paper presentations submitted by the authors and scrutinized by the editorial committee.
 Because of restrictions on travel and indoor activities related to COVID-19, we were forced to hold the conference online only. Attendees were notified well in advance that the on-site conference was changed to an online conference, where the timeline and order of the talks were defined. The video conference was held on the original set dates. Due to the large variety of topics and the relatively large number of attendees, the conference was separated into main and parallel sessions. Each plenary speaker gave an oral presentation of 30-40 minutes accompanied by his slides' material, allocated for questions and discussion.
 The organizing and editorial committees of IPIIS 2022 hope you can enjoy the reading of this volume. Additionally, we want to thank all authors and participants for providing their valuable contributions for these proceedings, as well as the reviewers for their constructive recommendations and feedback aiding to improve the presented articles.
 IPIIS Organizing Committee
 Zhengzhou, China

Students often face difficulties in grasping and un derstanding fundamental digital signal processing (DSP) concepts in the classroom environment. Most DSP courses do not have labs associated with them, and the ones that do typicall y depend on the usage of text-based programming languages (e.g., MATLAB) that do not allow real-time external hardware interaction. Although the availability of external DSP platforms (e.g. National Instruments Speedy-33, Texas Instruments DSP Student Kits, etc.) for educational purposes has increased because of recent advances in embedded processors and sensor technology, they are rarely used in early DSP courses because of the programming sophistication needed for real-time processing. In this paper we discuss the development of low-co st experimental DSP learning modules for classes that do not usually have a lab component. T hese modules use National Instruments' LabVIEW for their programming and development platform with the Speedy-33 DSP board and LEGO Mindstorms NXT Brick as the hardware platforms. Many of the modules can also be run completely on the host computer's sound card. Modules have been developed for examining different aspects of topics such as sampling, alias ing, and filtering, while working with data that has been captured and processed in real-time. Stud ents are able to interact with the hardware and data through GUIs, thus obviating the need to first develop real-time programming skills. This paper will describe these modules and how they are designed to be used both in lectures and as part of homework assignments.

TileCal is the central hadronic calorimeter of the ATLAS experiment at the LHC collider at CERN. The Read-Out Drivers (ROD) are the core of the off-detector electronics. The main components of the RODs are the Digital Signal Processor (DSP) placed on the Processing Unit (PU) dautherboards. This paper describes the DSP code and its performance with calibration and real data. The code is divided into two different parts: the first part contains the core functionalities and the second one the reconstruction algorithms. The core acts as an operating system and it controls the configuration, the data reception, transmission, online monitoring and the synchronization between front-end data and the Trigger information. The reconstruction algorithms implemented on the DSP are the Optimal Filtering (OF), Muon Tagging (MTag) and Missing ET (MET) calculation. The OF algorithm reconstructs the for each TileCal cell the amplitude and time of the deposited energy. This reconstructed energy is used by the MTag algorithm to tag low transverse momentum muons that may escape the ATLAS muon spectrometer Level 1 trigger whereas the MET algorithm computes the total transverse energy and the projection on X and Y for the entire module that will be used by the Level 2 trigger system. The DSP code performance has been validated with offline reconstruction comparison. The DSP performance has been evaluated using calibration data from Charge Injection System.

The H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In order to accelerate the decoding speed, several algorithmic optimisations have been ported to inverse entropy decoding and intra-prediction modules. The parallelism between algorithm execution and data transfers was fully exploited using Enhanced Direct Memory Access (EDMA) engine. Furthermore, based on the DSP architectural features, various core-specific optimisation techniques were adopted leading to an increase in speed by up to 70%. Intensive experimental tests prove that a real-time decoding on TMS320C6416 DSP running at 720 MHz is obtained for Common Intermediate Format resolution (CIF 352 × 288)

As a modelling and simulation tool, MATLAB/Simulink plays a significant role in industrial control design. To allow the deployment of the designed control solutions a number of code generation facilities have been developed, that aim on implementing PC-based control units or embedded controllers based on micro-controllers or digital signal processors (DSP). This has enabled MATLAB/Simulink to cover the model-based development process from conceptual design over simulative validation to rapid-prototyping (Krasner (2004)). Although not a new technology per se, since the first commercial field-programmable gate array (FPGA) has been released by Xilinx in 1985, recent development in the field of reconfigurable hardware has created FPGAs, the capabilities of which apply to the requirements of industrial control in a growing number of application domains (Monmasson & Cirstea (2007)). Therefore, also code generation facilities targeting FPGAs have emerged, that link the modelling level to the level of hardware description languages (HDL), from which the lower-level descriptions (RTL) and chip-specific implementations are derived using hardware synthesis tool chains.

The phase 1 upgrade of the ATLAS [1] pixel detector will be done by inserting a fourth pixel layer together with a new beampipe into the recent three layer detector. This new detector, the Insertable B-Layer (IBL) should be integrated into the recent pixel system with as few changes in services as possible, but deliver some advantages over the recent system. One of those advantages will be a new data transmission link from the detector modules to the off-detector electronics, requiring a re-design of the electro-optical converters on the off-detector side. First ideas of how to implement those, together with some ideas to reduce cost by increasing the systems throughput are discussed.

Disclosed is a stringed instrument (100) with embedded digital signal processing (DSP) modeling capabilities. The stringed instrument (100) has a body (102) and a plurality of strings (106) and each of the plurality of strings (106) is respectively coupled to a pickup of a polyphonic pickup (110). The polyphonic pickup (110) is used to detect a vibration signal for each string (106). An A/D converter converts the detected vibration signal of a string into a digital string vibration signal. Further, a digital signal processor (120) is located within the body of the stringed instrument to process the digital string vibration signal. Particularly, the digital signal processor (120) is used to process the digital string vibration signal such that the corresponding string tone of one of a plurality of selectable stringed instruments may be emulated. The emulated digital tone signal is then converted to analog form to create an emulated analog tone signal for output to an amplification device.

Because of the great improvements in computer engineering, digital signal processing has been getting more and more important in recent years. Since discrete transformations play a significant role in digital signal processing, they have found many applications in various fields. The discrete cosine transform (DCT) is well known for its usefulness in the fields of image processing and data compression. With recent advances in the ISDN, limited communication bandwidth has become a new bottleneck, a possible solution to which may be an efficient encoding algorithm/architecture. The paper presents a two-stage algorithm and its corresponding architectures for efficient computation of a power-of-two length DCT. In this approach, the transform matrix of the DCT is decomposed into the product of two matrices, the preprocessing and the postprocessing ones. The elements in the preprocessing stage consist of 1, −1, and 0 only; the postprocessing stage is of block diagonal form in which each block performs a circular-convolution-like (CCL) operation. Thus, both stages can be implemented efficiently either by software or hardware. Details of the matrix decomposition are described and several corresponding architectures are also presented.

A new approach to fiber optic sensing is proposed which combines the multi-parameter sensing capabilities of standard optical fibers with recent advances in demodulation schemes and digital signal processing (DSP) for coherent optical communication systems. A common HW that can fulfil multi-purpose monitoring requests is obtained, where the information related to a specific physical parameter is recovered through a proper tailoring of the DSP. The fiber optic sensor thus becomes Software-Defined by the customer specific requirements, proving a cost-effective and versatile diagnostic solution for the achievement of sustainable predictive maintenance strategies in the manufacturing industry.

Power grids are actually more complex in their structure and in the requirements that they must satisfy, including perfect sinusoidal wave without outages and transitory over-voltages. Among the faults that can occur in the distribution networks, high impedance and arc faults are the most persistent and difficult to solve. Recent advances in digital technology have enabled practical solutions for fast detection of a high percentage of these previously undetectable faults. In this paper, a new approach for high impedance arc faults detection is presented. It is possible, by using a Digital Signal processor (DSP), to conceive a system able to detect the presence of unwanted and alarming frequencies in the distribution network. These particular frequencies are generated by electrical arcs occurring in the network. Finally, experimental and simulation results are provided to validate the performance of the digital implementation.

Digital signal processing (DSP) combined with coherent detection has played a central role in the recent capacity expansion of optical networks. Optical superchannels aim to increase per-channel interface rates as well as per-fiber capacities of wavelength-division multiplexed (WDM) systems in a cost-effective manner. Superchannels circumvent the electronic bottleneck via optical parallelism and provide high-per-channel data rates and better spectral utilization, especially in transparent optical mesh networks. This article reviews recent advances in the generation, detection, and transmission of optical superchannels with channel data rates on the order of terabits per second (Tb/s). Enabling DSP techniques such as Nyquist-WDM, orthogonal frequency-division multiplexing (OFDM), software-defined modulation and detection, advanced coding, and joint DSP among the superchannel constituents are presented. Future prospects of DSP techniques for high-capacity superchannel transmission are also discussed.

To find solution for XOR problem we are considering two widely used software that is being relied on by many software developers for their work. The first software is Google Colab tool which can be used to implement ANN programs by coding the neural network using python. This tool is reliable since it supports python language for its implementation. The other major reason is that we can use GPU and TPU processors for the computation process of the neural network. The major advantage of this is that for complex Neural Networks instead of using CPU present in the user’s system we can use those two processors through online mode without purchasing such processors for our computation. The next software that can be used for implementing ANN is Matlab Simulink. This software is used for highly calculative and computational tasks such as Control System, Deep Learning, Machine Learning, Digital Signal Processing and many more. Matlab is highly efficient and easy to code and use when compared to any other software. This is because Matlab stores data in the form of matrices and computes them in this fashion. Matlab in collaboration with Simulink can be used to manually model the Neural Network without the need of any code or knowledge of any coding language. Since Simulink is integrated with Matlab we can also code the Neural Network in Matlab and obtain its mathematically equivalent model in Simulink. Also, Matlab has a dedicated tool in its library to implement neural network called NN tool. Using this tool, we can directly add the data for input, desired output, or target. After inserting the required data, we can train the network with the given dataset and receive appropriate graph’s which will be helpful in analyzing the data. Once the Neural Network is trained, we can test the network through this tool and verify the obtained results.

A Kalman filter for estimating the state of a disk drive head-positioning mechanism has been implemented on a Texas Instruments TMS320C25 digital signal processor (DSP). The predictive formulation of the Kalman filter is employed to avoid potential difficulties with computational delays. Quantization effects of the filter are measured by comparing the performance of the 16—bit fixed—point DSP filter with a 64—bit floating point filter implemented on a general purpose computer. Results of the implementation show that the Kalman filter uses less than two percent of the computational bandwidth of the DSP at a sample period of 250 μS, leaving more than ninety-eight percent available for executing the control algorithm and other tasks.

This paper addresses the substantial workload associated with traditional digital signal processor (DSP) motor control software development by proposing a method to automatically generate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{C}$</tex> code from system models using the Simulink modeling platform, thereby significantly reducing the motor control development cycle. The working principles and development framework of the automatic code generation technology based on Model-Based Design (MBD) are first elucidated. Subsequently, a Space Vector Pulse Width Modulation (SVPWM) algorithm simulation model is established within Simulink. Finally, the generated code is deployed onto a DSP control system hardware platform for experimental validation. The results demonstrate that the application of MBD enables rapid DSP code generation, improves motor development efficiency, and achieves the desired control performance.

Field Programmable Gate Arrays (FPGAs) provide flexible computational architectures that are ideal for digital signal processing (DSP). With support of a NIH/NIDCD SBIR grant, we are developing an open FPGA platform for the speech, hearing, and acoustics research communities. The advantage of using FPGAs in a computational platform over conventional CPU approaches is the ability to implement low-latency high-performance signal processing with deterministic latencies. The hardware portion of the platform includes an audio codec and an Intel System-on-Chip (SoC) FPGA that contains ARM CPUs alongside the computational fabric that allows custom data plane designs. Development uses Mathwork’s Simulink that allows exploration and simulation of signal processing algorithms. Once a Simulink model has been developed to implement audio processing in either the time domain or frequency domain, VHDL code can be generated that implements the desired signal processing. The VHDL code is then implemented in the FPGA computational fabric where the FPGA functions as a real-time signal processor. We are currently soliciting ideas/feedback from the speech, hearing, and acoustic communities as to what features they would like to see in the next iteration of the open FPGA-based computational platform. [NIH/NIDCD R44DC015443: www.openspeechtools.com]