A rotary magazine‐based dynamic pick‐and‐place approach for robotic PCB assembly

Printed circuit board (PCB) assembly lines consist of a number of different machines for mounting electronic components onto PCBs. While high-speed placement machines are employed to assemble standard components, so-called fine-pitch placement machines are used to mount complex electronic components with high precision and by use of specific nozzles. In this paper, we investigate a typical mass production environment where a single type of PCB is assembled in a line comprising high-speed as well as high-precision placement machines. The PCB assembly line balancing problem consists of assigning component feeders, each holding a specific electronic component type, and the corresponding placement operations to machines in the line so as to minimize the assembly cycle time. To solve this problem, a two-stage solution procedure based on genetic algorithm (GA) is proposed. In the first stage, component feeders are assigned to the placement machines with the objective of balancing the workload within the assembly line. A number of candidate solutions are then transmitted to the second stage, where specific machine optimization algorithms are applied to determine the feeder-slot assignment in the component magazine of the machines and the placement sequence of the various components. As a result, fine-tuned placement operation times are achieved which reflect the individual operation mode and the actual component setup of the placement machines. Finally, from the candidate solutions the one which minimizes the actual PCB assembly time is selected.

Production planning and control of the printed circuit board (PCB) assembly includes several decisions dealing with, for example, grouping of PCB jobs, allocation of PCB batches to machine lines, sequencing of batches and load balancing of lines. The production time of a PCB job for a given placement machine is a key factor in this context and it must be quickly and accurately estimated, possibly millions of times in a single planning task, to avoid erroneous decisions. The commonly used nominal tact time-based estimators are very rough and the machine simulators too slow. Therefore, the purpose of this study is to give better machine-specific estimators that avoid the construction the actual machine control program. Two new estimators are proposed for gantry machines, one based on the information given by the manufacturer about the operations of the placement head, and the other on the regularised least-squares regression method trained with a set of PCB placement jobs. In practical evaluation with 95 PCB jobs, the mean absolute percentage error of the first and second methods are 3.75% and 6.52%, respectively, while that of the tact time-based approach is more than 17%. This indicates a great potential of the proposed methods as production time estimators.

In recent years, the development of low cost consumer electronic products such as television, mobile, washing machine etc. make high demands on manufacturing of defect free Printed Circuit Board and Printed Circuit Board Assembly. Therefore, it is necessary to know the different types of defects and defect detection techniques of Printed Circuit Board in order to produce high quality zero defect printed circuit boards. This paper discusses various methods which have been used in detecting defects so as to understand the gaps which would be helpful for the researchers to do the future work related to defect detection.

Recent technological innovations, namely the development of new solder pastes with increased tack life and the introduction of bypass conveyors, facilitate the use of mixed-model lines in printed circuit board (PCB) assembly. This paper presents a simulation study comparing PCB assembly lines operating in conventional batch and in mixed-model assembly mode. For the latter case, a novel group setup strategy is developed. In the first stage, component types and placement operations for each type of PCB are assigned to the machines in the assembly line with the objective of balancing the workload. In the second stage, PCB types with similar component requirements are clustered into setup families. In addition, the feeder-slot assignment for each setup family and the sequence of placement operations for each PCB type are determined. In the final stage, a cyclical mixed-model production schedule is established. The performance of the proposed solution approach is evaluated by means of a simulation study. Two alternative material flow systems are investigated: a serial conveyor which directly links one machine to the other and a flexible one that allows to bypass downstream machines in the line.

A knowledge-based system (or an expert system) embodies a domain expert’s knowledge and problemsolving strategy. Domain specific knowledge-based systems formalise the complicated set of informal procedures understood by experts alone and make the expertise available to a wide range of people. Knowledgebased systems have been developed and used in fields as diverse as medicine, mineral exploration, and chemistry. They have been used in various engineering applications and extensively in manufacturing. This paper reviews the application of knowledge-based systems in the Printed Circuit Board (PCB) assembly domain. In keeping with the initial development of knowledgebased systems in the field of manufacturing, most of the current applications of knowledge-based systems in PCB assembly address issues related to process planning. This trend can be attributed to the diversity and short life cycles of electronic products, and shortage of human expertise. A few systems have been developed for PCB design. Developments in the field of electronics packaging and industry predictions lead us to believe that knowledge-based systems will be developed for many more applications within the field.

Reducing the time it lakes to place components on to printed circuit boards (PCBs) is a major robotic assembly objective. This paper explores a robot control approach featuring dynamic choice of pick-and-place points for retrieving and inserting components. In this concept, the component magazine and PCB tray both move to calculated points that minimize the overall robotic assembly time. Compared with that of another approach which employs fixed positions for retrieval and insertion, the new approach avoids robot waiting time. The same assembly sequence and component magazine assignment was used to test the difference between these two approaches. In both models, the PCB worktables and magazine are assumed to be mobile and to move at constant velocity between points. Experimental results showed that the proposed dynamic pick-and-place (DPP) approach is superior to the fixed pick-and-place (FPP) approach in nearly all cases.

This paper investigates a multi-stage hybrid flow shop scheduling problem in a real-world printed circuit board (PCB) assembly shop. Some distinct characteristics such as calendar constraints, sequence-dependent setup times, unrelated parallel machines and stage skipping are taken into account. Besides, lot-sizing is introduced to split an order of PCBs into a number of smaller sub-lots to improve the utilization of the assembly lines. This article develops an effective hierarchical approach to reduce the complexity of such a complicated PCB scheduling problem by decomposing it into two highly coupled sub-problems of job sequencing and batch scheduling with lot-sizing. A two-stage ant colony algorithm with lot-sizing is proposed to evolve best results for makespan criterion. Extensive computational experiments have been conducted to compare the performance with two other algorithms. The results demonstrate that the proposed two-stage ant colony algorithm with lot-sizing is competitive in terms of computational result, computational time and stability.

Process planning is a critical function in any manufacturing domain. This is especially true in the electronics manufacturing area where substantial heuristic and experiential knowledge is commonly used during process plan development. While research in computer-aided process planning (CAPP) has tended to concentrate in the machining realm, few CAPP systems have been developed for electronics manufacturing applications and more specifically for the printed circuit board (PCB) assembly domain. Besides, the CAPP systems that have been developed for this area have dealt with either insertion mount or surface mount PCB assembly processes only.

A production scheduling problem for printed circuit board (PCB) assembly with multiple lines is addressed. The investigated problem is to schedule a set of PCB assembly jobs with different ready times and due dates on multiple assembly lines, with the objective to minimize the sum of total weighted tardiness of jobs and weighted makespan. The feature that each job can be completed by different lines with different process times makes the problem a special type of unrelated parallel-machine scheduling problem (PMSP) with special constraints and a unique objective. A mixed-integer linear programming model for the problem is established and verified through solving some small-sized problem instances to optimality. In order to solve the real-world problems, a steady-state genetic algorithm with an improved replacement strategy is proposed. Experimental tests and a case study are conducted to examine the usefulness and effectiveness of the approach.

10 - Dynamic deformation of a printed circuit board in drop-shock

The rapid development of information and communication technologies has driven the rapid growth of data traffic and the large requirement of high-speed optical transceiver modules. Usually, optical subassemblies through flexible printed circuit boards (PCBs) connect with the hard PCBs to compose as optical transceiver modules. Because of the impedance mismatch of connection between flexible PCB and hard PCB, the operation bandwidth of the module can be limited. In this paper, the design of connection between flexible PCB and hard PCB in optical subassembly modules will be investigated for increasing the operation speed of the module. First, the transmission bandwidth of flexible PCB is analyzed. High-frequency performances of three transmission line structures, micro-strip line, grounded coplanar waveguide, and top ground micro-strip line, are investigated in flexible PCB. High-frequency performances of flexible PCB with different bending types are also investigated. The flexible PCB has been verified to be suitable to use in 25 Gb/s applications. Next, the high-speed transmission performance is analyzed through the connection between flexible PCB and hard PCB, because the impedance mismatch usually occurs at the connection. The ground pads are added near the signal line of flexible PCB, and the ground pads are connected to the ground layer in PCB through ground vias. The anti-pad in hard PCB is added under the signal solder pad. The dip of S21 response can be eliminated by the optimized ground pad. The impedance mismatch can be reduced by the optimized anti-pad, the impedance increases from 40-Ω to 49-Ω at the connection between flexible PCB and hard PCB, and the transmission bandwidth can increase from 16.5 GHz to 23.5 GHz. TO-46 header is a common and low-cost packaging solution for DFB laser and photodiodes. The connection between flexible PCB and TO-46 header is also investigated. While the connection has a gap, the dip of frequency response will occur at lower frequency. While the connection is very close, the bandwidth can be larger than 25 GHz. The flexible PCB, hard PCB, and TO-46 header are combined together, and the 23 GHz transmission bandwidth can be obtained. The 25 Gb/s transmission eye diagram is also measured, and the eye height, rise time, fall time, and Q-factor are 268.14 mV, 13.78 ps, 13.56 ps, and 8.76, respectively. The combined flexible PCB, hard PCB, and TO-46 header are verified to be suitable to apply in 25 Gb/s optical subassembly modules, and will be able to be used in 100G Ethernet.

Process planning output can be post-processed into criteria for job scheduling decisions in printed circuit board assembly using surface-mount technology (SMT). Artificial intelligence-based techniques used in computerized planning and scheduling systems in other industries can be extended to printed circuit board operations. These techniques include blackboard architectures, object-oriented programming systems, and nonmonotonic reasoning systems. These techniques were used to demonstrate a unique architecture of blackboard systems that communicate via object-oriented messages to arrive at a shop-floor process plan and production schedule. The methodology was specialized to the assembly of printed circuit boards using surface-mounted components in a high-variety/low-volume product mix. The assembly facility was represented as a hierarchical object of product, process, and organizational knowledge. The system of working heuristics was integrated within a prototype environment with the practitioners that assisted in its development. The end result is a good working methodology for system development, implementation, and maintenance by knowledge worker involvement.

A heuristic-based model (HBM) that emulates the decision-making process involved in microsequencing components for printed circuit board (PCB) assembly is presented. The model uses a heuristic approach that combines the computer power with the reason

The objective of this research is to reduce the defects in the manufacturing of Printed Circuit Board (PCB) Assembly according to the case study company's issue. The defects from this process must be repaired by the operator and the repairing process becomes waste. The defects occur from the PCB assembly with the Reflow soldering process. The Six Sigma approach with the Design, Measure, Analyze, Improve, and Control (DMAIC) methodology is applied to define the problem and make the main problem focused. The defects are collected as data from the Daily Process Confirmation Record. The cause-and-effect diagram is used to clarify the possible factors to examine. Furthermore, the Design of the Experiment is applied to analyze the significant factors that cause the defects. The 2k Centre points design is used to test the significance of factors. It is observed that after changing only one factor, i.e. solder paste's preparation, the defects are reduced from 5.80% to 0.00%. Not only are the defects reduced significantly but also the man-hour is reduced too. Furthermore, it is anticipated that the repair time will be reduced from 116 hours to less than 50 hours.

Selecting products that have been qualified by industry standards for use in printed circuit board assembly processes is an accepted best practice. That products which have been qualified, when used in combinations not specifically qualified, may have resultant properties detrimental to assembly function though, is often not adequately understood. Printed circuit boards, solder masks, soldering materials (flux, paste, cored wire, rework flux, paste flux, etc.), adhesives, and inks, when qualified per industry standards, are qualified using very specific test methods which may not adequately mimic the assembly process ultimately used. It is recommended that products used in combination on a printed circuit assembly be qualified in combination to the extent necessary to provide a full understanding of interactions that may occur in the product. IPC J-STD-001 provides good guidance with regards to process validation testing although said testing is limited to the Appendix of the document. J-STD-001D, Appendix C focuses on process validation via Surface Insulation Resistance (SIR) Testing. The limitation to relying solely on SIR testing is its inherent inability to detect possible assembly issues which could result from employed combinations of printed circuit boards, solder masks, soldering materials (flux, paste, cored wire, rework flux, paste flux, etc.), adhesives, and inks. The authors’ intention with this paper is to describe two Designs of Experiments (DOE’s) that were developed for process validation. The first relies on SIR testing as the sole means of qualifying the final assembly. The second explores the use of a broad range of tests chosen to closely represent the end use application. DOE #1 was based upon the SIR testing procedure as per ANSI/J-STD-004, IPC-TM-650 2.6.3.3A the method which is also specified in J-STD-001. The scope of the test method is to determine the degradation of electrical insulation resistance of PCB specimens after exposure to specified materials. Since during the normal manufacturing process, a board assembly is exposed to a number of chemicals, for this DOE the standard SIR test coupons were prepared in such a way as to mimic a “typical” chemical mix that a board assembly may come in contact with during assembly. This involved applying the appropriate chemicals in the typical process order using appropriate process conditions.