Estimating the production time of a PCB assembly job without solving the optimised machine control

Printed circuit board (PCB) assembly lines consist of a number of different machines for mounting electronic components onto PCBs. While high-speed placement machines are employed to assemble standard components, so-called fine-pitch placement machines are used to mount complex electronic components with high precision and by use of specific nozzles. In this paper, we investigate a typical mass production environment where a single type of PCB is assembled in a line comprising high-speed as well as high-precision placement machines. The PCB assembly line balancing problem consists of assigning component feeders, each holding a specific electronic component type, and the corresponding placement operations to machines in the line so as to minimize the assembly cycle time. To solve this problem, a two-stage solution procedure based on genetic algorithm (GA) is proposed. In the first stage, component feeders are assigned to the placement machines with the objective of balancing the workload within the assembly line. A number of candidate solutions are then transmitted to the second stage, where specific machine optimization algorithms are applied to determine the feeder-slot assignment in the component magazine of the machines and the placement sequence of the various components. As a result, fine-tuned placement operation times are achieved which reflect the individual operation mode and the actual component setup of the placement machines. Finally, from the candidate solutions the one which minimizes the actual PCB assembly time is selected.

Printed Circuit Boards (PCBs) are widely used in most electronic devices. Typically, a PCB design has a set of components that needs to be assembled. In a broad sense, this assembly task involves placing PCB components at designated location on a PCB board; fixing PCB components; and testing the PCB after assembly operation to ensure that it is in proper working order. The stringent requirements of having a higher component density on PCBs, a shorter assembly time, and a more reliable product prompt manufacturers to automate the process of PCB assembly. Frequently, a few placement machines may work together to form an assembly line. Thus, the application of more than one machine for component placement on a PCB presents a line-balancing problem, which is basically concerned with balancing the workload of all the machines in an assembly line. This paper describes the application of a new artificial intelligence technique known as the immune algorithm to PCB component placement as well as the line balancing of PCB assembly line. It also includes an overview of PCB assembly and an outline of the assembly line balancing problem. Two case studies are used to validate the IA engine developed in this work. The details of IA, the IA engine and the case studies are presented.

A production scheduling problem for printed circuit board (PCB) assembly with multiple lines is addressed. The investigated problem is to schedule a set of PCB assembly jobs with different ready times and due dates on multiple assembly lines, with the objective to minimize the sum of total weighted tardiness of jobs and weighted makespan. The feature that each job can be completed by different lines with different process times makes the problem a special type of unrelated parallel-machine scheduling problem (PMSP) with special constraints and a unique objective. A mixed-integer linear programming model for the problem is established and verified through solving some small-sized problem instances to optimality. In order to solve the real-world problems, a steady-state genetic algorithm with an improved replacement strategy is proposed. Experimental tests and a case study are conducted to examine the usefulness and effectiveness of the approach.

Recent technological innovations, namely the development of new solder pastes with increased tack life and the introduction of bypass conveyors, facilitate the use of mixed-model lines in printed circuit board (PCB) assembly. This paper presents a simulation study comparing PCB assembly lines operating in conventional batch and in mixed-model assembly mode. For the latter case, a novel group setup strategy is developed. In the first stage, component types and placement operations for each type of PCB are assigned to the machines in the assembly line with the objective of balancing the workload. In the second stage, PCB types with similar component requirements are clustered into setup families. In addition, the feeder-slot assignment for each setup family and the sequence of placement operations for each PCB type are determined. In the final stage, a cyclical mixed-model production schedule is established. The performance of the proposed solution approach is evaluated by means of a simulation study. Two alternative material flow systems are investigated: a serial conveyor which directly links one machine to the other and a flexible one that allows to bypass downstream machines in the line.

This paper considers the operation of an electronic component placement machine. We developed a new feeder setup planning algorithm for a turret-type placement machine to increase productivity of printed circuit board (PCB) assembly. It is based on offline setup strategy which exploits a feeder hot-swapping mechanism of the placement machine. The proposed algorithm is examined by real-life PCB data. The productivity by the offline setup strategy is compared to those of unique setup and group setup strategy. It is shown that our algorithm achieves significant improvement in productivity.

This paper investigates a multi-stage hybrid flow shop scheduling problem in a real-world printed circuit board (PCB) assembly shop. Some distinct characteristics such as calendar constraints, sequence-dependent setup times, unrelated parallel machines and stage skipping are taken into account. Besides, lot-sizing is introduced to split an order of PCBs into a number of smaller sub-lots to improve the utilization of the assembly lines. This article develops an effective hierarchical approach to reduce the complexity of such a complicated PCB scheduling problem by decomposing it into two highly coupled sub-problems of job sequencing and batch scheduling with lot-sizing. A two-stage ant colony algorithm with lot-sizing is proposed to evolve best results for makespan criterion. Extensive computational experiments have been conducted to compare the performance with two other algorithms. The results demonstrate that the proposed two-stage ant colony algorithm with lot-sizing is competitive in terms of computational result, computational time and stability.

Electronics manufacturers use robots extensively in printed circuit board (PCB) assembly to attain high product quality at low production times. In robotic PCB assembly, fixed pick‐and‐place (FPP) causes unnecessary waste of time. A former paper explored the dynamic pick‐and‐place (DPP) approach to avoid robot waiting time and thus reduce robotic PCB assembly time. To further decrease robot moving or working space when the DPP approach is applied, this paper presents the rotary magazine‐based DPP approach. Experimental results show that the proposed approach not only reduces robot working space, but also reduces assembly time. The more insertions and component types, the more the assembly time is reduced.

A knowledge-based system (or an expert system) embodies a domain expert’s knowledge and problemsolving strategy. Domain specific knowledge-based systems formalise the complicated set of informal procedures understood by experts alone and make the expertise available to a wide range of people. Knowledgebased systems have been developed and used in fields as diverse as medicine, mineral exploration, and chemistry. They have been used in various engineering applications and extensively in manufacturing. This paper reviews the application of knowledge-based systems in the Printed Circuit Board (PCB) assembly domain. In keeping with the initial development of knowledgebased systems in the field of manufacturing, most of the current applications of knowledge-based systems in PCB assembly address issues related to process planning. This trend can be attributed to the diversity and short life cycles of electronic products, and shortage of human expertise. A few systems have been developed for PCB design. Developments in the field of electronics packaging and industry predictions lead us to believe that knowledge-based systems will be developed for many more applications within the field.

In recent years, the development of low cost consumer electronic products such as television, mobile, washing machine etc. make high demands on manufacturing of defect free Printed Circuit Board and Printed Circuit Board Assembly. Therefore, it is necessary to know the different types of defects and defect detection techniques of Printed Circuit Board in order to produce high quality zero defect printed circuit boards. This paper discusses various methods which have been used in detecting defects so as to understand the gaps which would be helpful for the researchers to do the future work related to defect detection.

Process planning is a critical function in any manufacturing domain. This is especially true in the electronics manufacturing area where substantial heuristic and experiential knowledge is commonly used during process plan development. While research in computer-aided process planning (CAPP) has tended to concentrate in the machining realm, few CAPP systems have been developed for electronics manufacturing applications and more specifically for the printed circuit board (PCB) assembly domain. Besides, the CAPP systems that have been developed for this area have dealt with either insertion mount or surface mount PCB assembly processes only.

One of the most important factors to give an inspection automation decision is the precision of measurements taken by the inspection machine. This paper aims to provide help in the selection of an automatic optical inspection (AOI) machine for a printed circuit board (PCB) assembly line of an electronics manufacturer. Since the visual inspection of soldered surfaces on a PCB is a crucial step, AOI machines bring great speed and accuracy to the inspection process. The main goal is to find the best automatic inspection machine alternative among the three AOI machine offerings according to nine selection criteria by integrating coefficient of variation statistic with TOPSIS and VIKOR, which are well-known multicriteria decision analysis methods. For this purpose, three different brands of AOI machines have been tested for the same PCBs, with 10 different components. After calculation of TOPSIS and VIKOR rank scores, the coefficient of variation of rank scores for all components is obtained and the selection of the AOI machine is finalized.

10 - Dynamic deformation of a printed circuit board in drop-shock

In this paper, we consider a repetitive routing problem which we find on a printed circuit board assembly line. There are m different printed circuit boards to be processed. As an automated manipulator embeds electronic parts in a printed circuit board from above, n identical pins from underneath protect it against overbending. A dedicated pin configuration is designed for each printed circuit board so that pins do not obstruct its own circuit. A single grasp-and-delivery robot transfers the pins one by one to arrange them from a configuration to another one. Given an initial configuration of pins and a permutable set of m required configurations, our repetitive routing problem asks to find a configuration sequence, i.e., a processing order of m printed circuit boards, and a transfer route of the grasp-and-delivery robot so that the route length over all m transitions is minimized. We first design a polynomial time approximation algorithm with factor four to a restricted version of the repetitive routing problem with a non-permutable set of configurations, i.e., with a fixed processing order of m printed circuit boards. Applying the procedure, we then show that the repetitive routing problem with a permutable set of configurations admits a polynomial time approximation algorithm with factor six.

Printed circuit boards (PCB)and SMD packages are made from different materials which coefficients of thermal expansion can differ much. Hence, under thermal load, e.g. board assembly or at field conditions, PCB and package deformation and deviation from the initial state often occur as warpage. During board assembly this warpage can cause failures such as open solder joints and/or shorts of solder joints. In this paper, the use the of shadow moire technique will be introduced for capturing the warpage under thermal loads. Measurement results of single substrates and a selected BGA package will be shown. Furthermore, a design process for PCBs to be applied for investigation of the influence of assembly process parameter will be described. It is assumed that the applied variations and their influence on the assembly quality are linked by the equilibrium of mechanical forces between PCB, BGA and solder joint. Additionally, it is assumed that mechanical stress - especially in out-of-plane direction-may occur in the solder joints. These thoughts apply for soldering process as well as temperature cycling conditions. A finite element model was implemented to analyze the stress for the selected BGA under defined conditions and to investigate warpage impacts on reliability. Finally, a novel approach to measure the electrical functionality will be introduced addressing BGAs under test which come with a high number of connections.

Selecting products that have been qualified by industry standards for use in printed circuit board assembly processes is an accepted best practice. That products which have been qualified, when used in combinations not specifically qualified, may have resultant properties detrimental to assembly function though, is often not adequately understood. Printed circuit boards, solder masks, soldering materials (flux, paste, cored wire, rework flux, paste flux, etc.), adhesives, and inks, when qualified per industry standards, are qualified using very specific test methods which may not adequately mimic the assembly process ultimately used. It is recommended that products used in combination on a printed circuit assembly be qualified in combination to the extent necessary to provide a full understanding of interactions that may occur in the product. IPC J-STD-001 provides good guidance with regards to process validation testing although said testing is limited to the Appendix of the document. J-STD-001D, Appendix C focuses on process validation via Surface Insulation Resistance (SIR) Testing. The limitation to relying solely on SIR testing is its inherent inability to detect possible assembly issues which could result from employed combinations of printed circuit boards, solder masks, soldering materials (flux, paste, cored wire, rework flux, paste flux, etc.), adhesives, and inks. The authors’ intention with this paper is to describe two Designs of Experiments (DOE’s) that were developed for process validation. The first relies on SIR testing as the sole means of qualifying the final assembly. The second explores the use of a broad range of tests chosen to closely represent the end use application. DOE #1 was based upon the SIR testing procedure as per ANSI/J-STD-004, IPC-TM-650 2.6.3.3A the method which is also specified in J-STD-001. The scope of the test method is to determine the degradation of electrical insulation resistance of PCB specimens after exposure to specified materials. Since during the normal manufacturing process, a board assembly is exposed to a number of chemicals, for this DOE the standard SIR test coupons were prepared in such a way as to mimic a “typical” chemical mix that a board assembly may come in contact with during assembly. This involved applying the appropriate chemicals in the typical process order using appropriate process conditions.