A scalable instruction buffer and align unit for xDSPcore

The emerging applications have imposed strong requirements, such as high processing capacity, low‐power consumption, reduced size and many others, on the sensor‐based systems. Owing to their balanced combination of flexibility and hardware performance, digital signal processors (DSPs) have become more and more popular used in sensor‐based systems. Many DSPs have adopted very long instruction words (VLIW) style architecture, for its ability to greatly enhance instruction level parallelism. However, as VLIW codes are statically scheduled, the behaviour of VLIW architecture is dominated by the efficiency of its compiler. Single instruction multiple data (SIMD) instructions, which perform multiple operations in parallel on multiple data packed in registers, have been widely used in DSPs to meet the requirements of sensor‐based systems. Although hand programming still yields the best performing SIMD codes, it is both time consuming and error prone. Advanced compiler techniques to automatically generate SIMD instructions, are under urgent demand. In this study, the authors proposed an SIMD code auto generation approach for VLIW architecture. It recognises candidates of operations in the intermediate representation, evaluates the possibility of grouping them into SIMD code, reconstructs the verified ones according to the cost model and finally generates the SIMD code. The authors have implemented this approach in the compiler of a VLIW DSP named Magnolia, which is designed for sensor‐based systems. The results show that the authors’ approach is very efficient, and can largely enhance the performance.

Very Long Instruction Word (VLIW) processors are very popular in embedded and mobile computing domain. Use of VLIW processors range from Digital Signal Processors (DSPs) found in a plethora of communication and multimedia devices to Graphics Processing Units (GPUs) used in gaming and high performance computing devices. The advantage of VLIWs is their low complexity and low power design which enable high performance at a low cost. Scalability of VLIWs is limited by the scalability of register file ports. It is not viable to have a VLIW processor with a single large register file because of area and power consumption implications of the register file. Clustered VLIW solve the register file scalability issue by partitioning the register file into multiple clusters and a set of functional units that are attached to register file of that cluster. Using a clustered approach, higher issue width can be achieved while keeping the cost of register file within reasonable limits. Several commercial VLIW processors have been designed using the clustered VLIW model. VLIW processors can be used to run a larger set of applications. Many of these applications have a good Lnstruction Level Parallelism (ILP) which can be efficiently utilized. However, several applications, specially the ones that are control code dominated do not exibit good ILP and the processor is underutilized. Cache misses is another major source of resource underutiliztion. Multithreading is a popular technique to improve processor utilization. Interleaved MultiThreading (IMT) hides cache miss latencies by scheduling a different thread each cycle but cannot hide unused instructions slots. Simultaneous MultiThread (SMT) can also remove ILP under-utilization by issuing multiple threads to fill the empty instruction slots. However, SMT has a higher implementation cost than IMT. The thesis presents Cluster-level Simultaneous MultiThreading (CSMT) that supports a limited form of SMT where VLIW instructions from different threads are merged at a cluster-level granularity. This lowers the hardware implementation cost to a level comparable to the cheap IMT technique. The more complex SMT combines VLIW instructions at the individual operation-level granularity which is quite expensive especially in for a mobile solution. We refer to SMT at operation-level as OpSMT to reduce ambiguity. While previous studies restricted OpSMT on a VLIW to 2 threads, CSMT has a better scalability and upto 8 threads can be supported at a reasonable cost. The thesis proposes several other techniques to further improve CSMT performance. In particular, Cluster renaming remaps the clusters used by instructions of different threads to reduce resource conflicts. Cluster renaming is quite effective in reducing the issue-slots under-utilization and significantly improves CSMT performance.The thesis also proposes: a hybrid between IMT and CSMT which increases the number of supported threads, heterogeneous instruction merging where some instructions are combined using SMT and CSMT rest, and finally, split-issue, a technique that allows to launch partially an instruction making it easier to be combined with others.

The increasing use of digital signal processors (DSPs) in wireless communications and signal processing necessitates the optimization of compilers to support special hardware features. In this paper, we propose a compiler transformation method for zero overhead loop (ZOL). It supports very long instruction word (VLIW), internal branches and the loops whose iterative times are known at runtime and before execution. In addition, for fully exploiting the special architecture features common in DSPs, the compilation of ZOL transformation is optimized, which further reduces the execution time of loop-intensive applications. The method is implemented on Swift which is a DSP architecture with ZOL and VLIW. Experimental results on benchmark programs show that the proposed method is effective in improving performance.

This paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and have adopted some very sophisticated parallelism extraction techniques, namely very long instruction word (VLIW) and SIMD designs. The intention is to show a development path of digital signal processors (DSP) and focuses on their features that allow parallel processing of algorithms.

This paper is focused on the benefit of low-level programming of Digital Signal Processors (DSPs) with Very Long Instruction Word (VLIW) architecture. Specifically, the process of hardware resources allocation which is outlined in text and proved by basic matrix benchmarks. Compared to available library functions, the proposed results decrease the number of execution cycles by tens of percent for smaller matrix dimensions and help developers to solve critical parts of their applications in the instruction-level approach.

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1) a 4-way VLIW processor implemented in an FPGA, (2) large speedups through hardware functions, (3) a hardware/software interface with zero overhead, (4) a design methodology for implementing signal processing applications on this architecture, (5) tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to times that of software with an average times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data streams (SIMD) and reconfigurable architecture. Equipped with eight SIMD-controlled 16-bit datapaths which can also be reconfigured as two 32-bit datapaths, the DSP core can process both 16-bit and 32-bit data in parallel, showing high performance, especially in the applications preferring parallel data flow computations, such as image processing. The SIMD scheme is extended with the instant-scalability of datapaths (ISSIMD), which offers the DSP a capability of dimension-controllable vector processing, so that to provide flexibility for different embedded applications. A first prototype in 0.18-/spl mu/m CMOS technology has been fabricated, which achieves IGMACS performance at the clock of 125 MHz.

Assigning service requests in Voice-over-Internet gateway multiprocessors

In this paper a real time approach to reduce speckle noise and enhance structures in speckle corrupted ultrasound image is proposed. It utilizes nonlinear anisotropic diffusion for speckle removal and edge enhancement. Unlike the conventional anisotropic diffusion performed in four different directions, here diffusion is performed in eight different directions. The algorithm has been proficiently implemented using a low cost Texas Instruments (TI) Digital Signal Processor (DSP) of series TMS320C64x+. The approach speeds up the computation by utilizing the ability of Very Long Instruction Word (VLIW) processor to perform multiple operations in parallel. In addition, a new feature to select a Speckle Reduction Imaging (SRI) mode is introduced which facilitates different degree of smoothing depending on the requirement. The experimental results show that with an speckled input image of size 640 × 480 the algorithm is capable of supporting 105 frames per second (fps). This method also promises better image quality than window based filtering techniques [1]–[4].

Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in high-performance embedded applications such as digital signal processing. Software thread integration (STI) can often improve the performance of looping code in cases where software pipelining performs poorly or fails. This paper examines both situations, presenting methods to determine what and when to integrate.We evaluate our methods on C-language image and digital signal processing libraries and synthetic loop kernels. We compile them for a very long instruction word (VLIW) digital signal processor (DSP) -- the Texas Instruments (TI) C64x architecture. Loops which benefit little from software pipelining (SWP-Poor) speed up by 26% (harmonic mean, HM). Loops for which software pipelining fails (SWP-Fail) due to conditionals and calls speed up by 16% (HM). Combining SWP-Good and SWP-Poor loops leads to a speedup of 55% (HM).

We studied the efficient implementation of a motion estimation algorithm for H.264/AVC on TMS 320C64x, a VLIW (very long instruction word) SIMD (single instruction multiple data) digital signal processor. H.264 motion estimation algorithms demand much arithmetic operations especially because of the variable block size optimization. The SAD (sum of absolute difference) reuse method is chosen not only to reduce the computation but also to utilize the regular algorithmic structure, which is essential for efficient implementation in parallel and pipelined processors. We applied a few techniques, such as loop length increase for efficient software pipelining, multi-block SAD computation for reducing memory access overhead, block processing for cache miss minimization, and improved quarter-pixel processing. The implementation results show that a real-time implementation of ME for D1 size (720*480) video is possible using a 720 MHz TMS320C6416 digital signal processor.

Future European space missions are in critical need of a new digital signal processor (DSP) free of any International Traffic in Arms Regulations (ITAR) restrictions. We present a new, highly parallel, 8-slot Very Long Instruction Word (VLIW) DSP modeled in LISA, a high-level architecture description language. Necessary software development tools as well as a synthesizable hardware model are generated from this abstract model automatically, improving the productivity and stability significantly. To our best knowledge, it is the first processor aimed to be used in space modeled at a higher abstraction level than RTL. The synthesis of the generated VHDL code using a 180nm CMOS standard cell library results in an area of 380 kGates and shows an aggregated peak performance of 1.0 GOPS and 750 MFLOPS, outperforming the only available other option, Atmel's TSC21020F processor, by an order of magnitude.

Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances, a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using the full power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method is at least four times faster for 8, 16 and 32 bits CRC.

With increasing demands for performance by embedded systems, especially by digital signal processing (DSP) applications, embedded processors must increase available instructionlevel parallelism (ILP) within significant constraints on power consumption and chip cost. Unfortunately, supporting a large amount of ILP on a processor while maintaining a single register file increases chip cost and potentially decreases overall performance due to increased cycle time. To address this problem, some modern embedded processors partition the register file into multiple low-ported register files, each directly connected with one or more functional units. These functional unit/register file groups are called clusters. Clustered VLIW (very long instruction word) architectures need extra copy operations or delays to transfer values among clusters. To take advantage of clustered architectures, the compiler must expose parallelism for maximal functional-unit utilization, and schedule instructions to reduce intercluster communication overhead. High-level loop transformations offer an excellent opportunity to enhance the abilities of low-level optimizers to generate code for clustered architectures. This dissertation investigates the effects of three loop transformations, i.e., loop fusion, loop unrolling, and unroll-and-jam, on clustered VLIW architectures. The objective is to achieve high performance with low communication overhead. This dissertation discusses the following techniques: Loop Fusion This research examines the impact of loop fusion on clustered architectures. A metric based upon communication costs for guiding loop fusion is developed and tested on DSP benchmarks. Unroll-and-jam and Loop Unrolling A new method that integrates a communication cost model with an integer-optimization problem is developed to determine unroll amounts for loop unrolling and unroll-and-jam automatically for a specific loop on a specific architecture. These techniques have been implemented and tested using DSP benchmarks on simulated, clustered VLIW architectures and a real clustered, embedded processor, the TI TMS320C64X. The results show that the new techniques achieve an average speedup of 1.72-1.89 on five different clustered architectures. These techniques have been implemented and tested using DSP benchmarks on simulated, clustered VLIW architectures and a real clustered, embedded processor, the TI TMS320C64X. The results show that the new techniques achieve an average speedup of 1.72-1.89 on five different clustered architectures.

The performance of Very Long Instruction Word (VLIW) microprocessors depends on the close cooperation between the compiler and the architecture. This paper evaluates a set of important compilation techniques and related architectural features for VLIW machines. The evaluation is performed on a SPARC-based VLIW testbed where gcc-generated optimized SPARC code is scheduled into high-performance VLIW code. As a base scheduling compiler, we experiment with three core scheduling techniques including enhanced pipeline scheduling, all-path speculation, and renaming. We analyze the characteristics of the useful and useless ALUs in each cycle to see how many of those ALUs execute non-speculative operations, speculative operations, and copies, respectively. Then, we evaluate the following compilation techniques: software pipelining, loop unrolling, non-greedy enhanced pipeline scheduling, profile-based all-path speculation, trace-based speculation, renaming, restricted speculative loads, and memory disambiguation. Since we experiment on a uniform testbed based on a detailed analysis of ALUs, our evaluation provides an useful insight on the performance impact of these techniques.