A System for Detecting Failed Electronics Using Acoustics

The materials used in the field of printed circuit boards are becoming increasingly complex as they are common to make use of numerous combination of metallic and composite plies. The potential for utilization of circuit boards is generally verified through the numerical simulation, especially for the multilayer printed circuit boards with high electronic density. This paper provides a numerical model intended to describe numerically the behavior of multilayer multimaterial circuit boards. Two parts are considered in the developed model: one is elastic-plastic damaging model that is presented to describe the metallic ply in the multilayer circuit boards; another is degenerated bi-phase model that is presented to describe composite ply. With the combination of equivalent laminate (EQLAM) method, the degenerated bi-phase successfully models the woven glass-fiber/epoxy-resin composite ply. These two plies are the basic components of multilayer circuit boards. Meanwhile, with the verification of static tests and dynamic tests, the reliability of presented model is confirmed.

A description is given of the test concept and experimental validation of measurement techniques which exploit built-in-test (BIT) to simplify RF susceptibility measurements of complex digital integrated circuits (ICs) and printed circuit (PC) boards. The use of the BIT capability of VLSI devices and PC boards: (1) simplifies the hardware and software interfaces to the device-under-test; and (2) reduces the external test equipment requirements. A specific example is given as to how these techniques and procedures were applied to a self-testing Am2903 4-bit microprocessor slice test circuit. Test data are presented which demonstrate the feasibility of using BIT techniques to obtain susceptibility thresholds with a significant reduction in test complexity and external test equipment requirements. The limitations associated with using BIT techniques for susceptibility characterizations of ICs and PC boards are also addressed. >

A new approach to integrated circuit (IC) noise modeling using a single current source for the whole area below the IC on a printed circuit board (PCB) is proposed. This approach extends the frequency of application of similar models in the literature by focusing on the current and power injected into the region outside the IC perimeter. A new measurement equipment for IC electromagnetic compatibility tests above 1 GHz is proposed; the printed reverberation board (PRB). A statistical model for characterizing the PRB is presented and confirmed by measurement results. Limitations of the fabricated PRB prototype and possible improvements are discussed. A new random IC model that includes the random properties of the IC noise is introduced. A methodology to extract the IC model by means of the PRB is presented. An active test PCB has been designed and fabricated to verify the feasibility of the modeling and measurement methods. Measurement results corroborated the validity of the new measurement and modeling approaches on one side, and on the other side showed that further studies are required.

An innovative approach is described for diagnosing faults in printed circuit boards (PCB) and PCB components through the detection, analysis, and localization of electrical field changes that occur within and around the PCB. This method utilizes electromagnetic emissions (EME) originating from the PCB to determine circuit health. EME from rapidly changing voltages and currents within high-speed logic and other circuits have traditionally been seen as a problematic source of interference that must be eliminated to as great an extent as possible. However, changes within these emissions can be a highly significant indicator that a failure has occurred within a PCB component as well as within adjacent circuit card paths of the board itself. Further, the hardware and software requirements needed to capture and analyze these emissions are relatively simple in comparison to todaypsilas highly complex automatic test equipment. This unique approach involves analyzing electromagnetic emission signatures through automated means, and ascribing failures to the circuit board as a whole, as well as to the individual circuit board components.

The counterfeit parts, e.g. integrated circuits (ICs) and printed circuit boards (PCBs), have shown significant increase over the recent years. However, existing counterfeit detection techniques deal with IC or PCB separately. Hence cannot verify the authenticity of the electronic system as a whole. In this paper, we propose a novel methodology, named CIPA, which concurrently verifies the authenticity of both IC and PCB through extracting the signature pairs generated by ring oscillator (RO) array without/with PCB cavity resonance. Remote authentication is allowable by transmitting CIPA signatures between the verifier and system vendor. CIPA structure has shown insignificant area overhead (0.945% on average), when implemented on a number of benchmarks. Both CIPA and the benchmarks have been implemented on authentic and counterfeit FPGA systems, results giving 100% confidence in detecting counterfeit ones.

The electronic systems we find in almost every product today are implemented using integrated circuits (ICs) mounted on printed circuit boards (PCBs). Developing electronic systems is a challenging task due to complexity and miniaturization. A single IC can contain billions of transistors, which are smaller than ever. As a result more Design-for-Test (DfT) features, so called instruments, are embedded on-chip in modern ICs to handle and monitor various activities. Many defects are handled at IC manufacturing; however, there are many problems occurring after ICs are being mounted on PCBs. In many cases, it is unfortunately not possible to reproduce the problem when the electronic system is taken to a repair shop. These problems are known as No Trouble Found (NTF). One obstacle is the limited access to the on-chip DfT instruments that exist in most ICs. We will discuss access to on-chip DfT instruments through the life-time of electronic systems. We will focus on electronic systems using the IEEE 1687 standard.

This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

MIT Lincoln Laboratory is working towards the development of a tileable radar panel to satisfy multimission needs. A combination of custom and commercial off-the-shelf (COTS) Monolithic Microwave Integrated Circuits (MMICs) have been developed and/or employed to achieve the required system functionality. The integrated circuits (ICs) are integrated into a low cost T/R module compatible with commercial printed circuit board (PCB) manufacturing. Sixty-four of the transmit/receive (T/R) modules are integrated onto the aperture PCB in an 8 × 8 lattice. In addition to the T/R elements, the aperture PCB incorporates transmit and receive beamformers, power and logic distribution, and radiating elements. The aperture PCB is coupled with a backplane PCB to form a panel, the line replaceable unit (LRU) for the multifunction phased array radar (MPAR) initiative. This report summarizes the evaluation of the second iteration LRU aperture PCB and T/R element. Support fixturing was developed and paired with the panel to enable backplane functionality sufficient to support the test objectives.

This paper describes research and development efforts in the application of advanced optical techniques for prognostic analysis of printed circuit boards and their components. Current methods of automated electronic testing require development of costly unique test program sets (TPSs) for each type of board, and only return information related to the current performance characteristics. The use of laser diagnostics in circuit board testing can eliminate the need for TPSs, while identifying compromises in material integrity that leads to hard and soft component failures. Additionally, they may be applied to solve instances of retest OK (RTOK) and no-fault-found events. Our investigation has focused on terahertz (T-Ray) imaging, laser acoustics, and near-infrared (NIR) laser imaging. T-Ray imaging is an emerging laser-based technology characterized by the ability to see through layers of plastic to the embedded metal traces of a circuit board or to the die of an encapsulated microchip. Laser acoustics may be applied to monitor the integrity of solder joints, and NIR laser imaging may be used to identify damage within an integrated circuit (IC). We present the results of our investigation into the combined use of these techniques for fault diagnosis, as well as their relative potential in the electronics test industry.

Functional reuse of Integrated Circuits (IC) is effective to recover electronic utilities. Interfacial delamination may occur when the ICs are disassembled from scrapped Printed Circuit Board (PCB) and reduce reusability. In delamination analysis, viscoelasticity of moulding compound is a non-ignorable property as it reduces the stress. It is the purpose of this research to analyse the effect of stress relaxation before and during the disassembly. Results demonstrate the Stress Free Temperature (SFT) of the plastic IC package is raised several centi-degrees by a reflow process and hardly changed by long-time relaxation at room temperature. Stress relaxation with different heating rates in the disassembly causes a tiny difference of Energy Release Rate (ERR). Based on the results, it is recommended that high heating rate is used when it is below SFT and otherwise moderate heating rate is used. Furthermore, low peak temperature is the most important to avoid delamination.

Some high performance computing systems interconnect the microprocessor and the printed circuit board (PCB) using an integrated circuit (IC) socket. In these systems the socket provides a low resistance electrical connection when its contacts are compressed between the IC and the PCB pads. Obtaining and maintaining an acceptable contact resistance is essential for the seamless operation of these interconnects. The electrical resistance of an IC socket contact is a function of applied load, contact compression, and contact surface quality. To apply load to a socket (and compress the contact) a mechanical system is utilized which may consist of springs, screws, bolster plate, heat sink, and other components. The analysis of contact compression and contact resistance in an IC socket assembly is not a simple task. It requires extensive material characterization and testing. Due to rapid design, vendor selection cycles, sample size requirements, and cost, the physical testing to estimate the variability of contact resistance in socket assemblies is not feasible. Probabilistic methods such as finite element analysis (FEA) are used to overcome this obstacle. FEA provides the means to model the response of an assembly to compressive loads and variation in the mechanical load system components. An issue with this approach is that each finite element analysis run takes hours to execute, making it an impractical approach for evaluations that consider numerous parameters and parameter values. This paper describes how the response surface methodology (RSM) can be utilized to reduce the number of FEA runs that are required for the analysis of contact compression and contact resistance. Statistical distributions of the parameters of interest are constructed and used with RSM and Monte Carlo simulations to generate a transfer function. This function is evaluated thousands of times by means of Monte Carlo simulations to quantify the probability that the contact compression (and contact resistance) requirements may not be met, while considering manufacturing variability. The approach allows the virtual qualification of socket assemblies without resorting to expensive testing and prohibitive FEA computation cycles

The research object in the work is the printed circuit boards (PCB) Production technological process using the additive technology of photopolymer 3D printing. The existing problem is that the manufacturing process of single-sided and double-sided PCBs, simple in technology, from the third to the fifth accuracy class, requires the use of a large amount of consumables and technological equipment. In turn, this affects the cost of the product. The research subject is models and methods for manufacturing PCB using photopolymer 3D printing. In order to reduce the cost of materials: film or aerosol photoresist, as well as reduce the number of technological operations, applying photoresist and for the manufacture of PCBs stencils, it is proposed to use photopolymer 3D printing technologies for the manufacture of PCBs. The paper analyzes the costs of Plexiwire Resin Basic Orange Transparen photopolymer resin for the manufacture of single-sided PCBs and calculates the cost of the consumable (resin) compared to the costs of dry film photoresist. 60 % cost of consumables (photopolymer resin) compared to dry film photoresist for making single-sided PCBs. The work is aimed at determining the dependence of the geometric dimensions of the PСВs topology and the consumption of photopolymer resin on the technological parameters of photopolymer exposure. A regression correlation model of the dependence of resin consumption on exposure parameters has been developed and correlation coefficients have been calculated. It has been established that with an increase in the exposure time of the photopolymer resin, the consumption of the photopolymer resin increases and the deviation of the geometric dimensions of the PCBs topology increases, which in turn negatively affects the quality of the product. Therefore, using the obtained regression model, it is possible to calculate the influence of parameters on the PCB topology and reduce the deviation of conductor sizes and resin consumption.

The rapid development of information and communication technologies has driven the rapid growth of data traffic and the large requirement of high-speed optical transceiver modules. Usually, optical subassemblies through flexible printed circuit boards (PCBs) connect with the hard PCBs to compose as optical transceiver modules. Because of the impedance mismatch of connection between flexible PCB and hard PCB, the operation bandwidth of the module can be limited. In this paper, the design of connection between flexible PCB and hard PCB in optical subassembly modules will be investigated for increasing the operation speed of the module. First, the transmission bandwidth of flexible PCB is analyzed. High-frequency performances of three transmission line structures, micro-strip line, grounded coplanar waveguide, and top ground micro-strip line, are investigated in flexible PCB. High-frequency performances of flexible PCB with different bending types are also investigated. The flexible PCB has been verified to be suitable to use in 25 Gb/s applications. Next, the high-speed transmission performance is analyzed through the connection between flexible PCB and hard PCB, because the impedance mismatch usually occurs at the connection. The ground pads are added near the signal line of flexible PCB, and the ground pads are connected to the ground layer in PCB through ground vias. The anti-pad in hard PCB is added under the signal solder pad. The dip of S21 response can be eliminated by the optimized ground pad. The impedance mismatch can be reduced by the optimized anti-pad, the impedance increases from 40-Ω to 49-Ω at the connection between flexible PCB and hard PCB, and the transmission bandwidth can increase from 16.5 GHz to 23.5 GHz. TO-46 header is a common and low-cost packaging solution for DFB laser and photodiodes. The connection between flexible PCB and TO-46 header is also investigated. While the connection has a gap, the dip of frequency response will occur at lower frequency. While the connection is very close, the bandwidth can be larger than 25 GHz. The flexible PCB, hard PCB, and TO-46 header are combined together, and the 23 GHz transmission bandwidth can be obtained. The 25 Gb/s transmission eye diagram is also measured, and the eye height, rise time, fall time, and Q-factor are 268.14 mV, 13.78 ps, 13.56 ps, and 8.76, respectively. The combined flexible PCB, hard PCB, and TO-46 header are verified to be suitable to apply in 25 Gb/s optical subassembly modules, and will be able to be used in 100G Ethernet.

Modern integrated circuits (ICs) contain thousands of instruments to enable testing, tuning, monitoring, and so on. These on-chip instruments must be accessed through the ICs' life-time. However, when ICs are mounted on Printed Circuit Boards (PCBs), access from system-level is challenged due to complex system hierarchies with a multitude of interfaces. In this paper we enable access from system-level to chip-level instruments by proposing hardware, protocol, and communication schemes. We have validated our scheme by implementing a system with two ICs on a Field-Programmable Gate Array (FPGA) where each IC includes an IEEE Std. 1687 network, communication between ICs is with Serial Peripheral Interface (SPI) and communication with the outside is with Universal Asynchronous Receiver Transmitter (UART). In experiments we evaluate communication based on software (polling) and hardware (interrupt) as well as overhead in terms of transported data and needed area.

: General John M. Shalikashvili, former Chairman of the Joint Chiefs of Staff (CJCS) stated, nature of modern warfare demands that we fight as a joint team. This was important yesterday, it is essential today, and it will be even more imperative tomorrow. Joint Vision 2010 provides an operationally based template for the evolution of the Armed Forces for a challenging and uncertain future. It must become a benchmark for Service and Unified Command visions. Simply put, the key to success is working together. Yet the most powerful, progressive, technologically advanced nation in the world cannot see that combat development and acquisition done in a vacuum threatens this nation's success in the joint environment. The United States Marine Corps' current concept-based requirement process (CBRP) creates problems for joint battlefield operations and requires restructuring. If Joint Vision 2010 is going to come to fruition, the Marine Corps must stop developing service specific equipment without considering the joint ramifications. It must embrace the idea of the joint battlefield instead of the cooperative battlefield. The USMC must now wait and see if the CJCSI 3170 can change the culture and take the Corps into the purple future.