A trajectory control gate driver for Wide Band Gap devices in standard packages

In this paper, a feedback active gate driver (AGD) based on a multistage technique for improving the switching trajectory of silicon carbide (SiC) MOSFET devices is presented. The main purpose of this technique is to reduce the oscillations and overshoot in high-frequency with low switching losses. Besides, the gate driver is designed considering the current load variations with simple circuit structure. An AGD validation has been developed by using simulations. The results have shown the behaviour of the AGD and feasibility. Therefore, the AGD can reduce the oscillations to avoid electromagnetic interference (EMI) and also decrease the overshoots caused by high di/dt current and dv/dt voltage slopes. In addition, the tests showed that the proposed AGD can be developed with low switching losses in high-frequency applications and medium power.

This paper investigates an active gate driver (AGD) for an SiC-MOSFET. The source current feedback type active gate driver utilizes the reactive voltage of the source wire inductance as a negative feedback signal to regulate the source current di/dt. Recently, the improvement of the switching performance of the AGD is limited due to the feedback system bandwidth. In this paper, a high bandwidth current feedback type power operational amplifier is applied as the gate drive circuit. Switching characteristics of the conventional resistive gate driver and the active gate driver are experimentally investigated by a double pulse test setup. The switching setup condition is 700 V / 80 A. This paper describes the construction of the AGD circuit and the experimental results. The over-shoot and ringing of the Vds and Is are reduced by using the active gate driver. In addition, the switching loss is simultaneously reduced.

This paper investigates an active gate driver for a large capacity multi-chip SiC-MOSFET power module. The active gate driver utilizes the reactive voltage of the source wire inductance as the negative feedback signal of the gate voltage. In addition, the feedback stabilization design is included in the circuit. The switching characteristics of the conventional resistive gate driver and the active gate driver are experimentally investigated by a double pulse test setup. The switching setup condition is 800 V / 300 A. This paper describes the construction of the active gate driver circuit and the experimental results. The over-shoot and ringing of the Vds and Is are reduced by using the active gate driver. In addition, the switching loss is simultaneously reduced.

The trend in power electronic applications is to reach higher power density and higher efficiency. Currently, the wide band-gap devices such as silicon carbide MOSFET (SiC MOSFET) are of great interest because they can work at higher switching frequency with low losses. The increase of the switching speed in power devices leads to high power density systems. However, this can generate problems such as overshoots, oscillations, additional losses, and electromagnetic interference (EMI). In this paper, a novel active gate driver (AGD) for improving the SiC MOSFET switching trajectory with high performance is presented. The AGD is an open-loop control system and its principle is based on gate energy decrease with a gate resistance increment during the Miller plateau effect on gate–source voltage. The proposed AGD has been designed and validated through experimental tests for high-frequency operation. Moreover, an EMI discussion and a performance analysis were realized for the AGD. The results show that the AGD can reduce the overshoots, oscillations, and losses without compromising the EMI. In addition, the AGD can control the turn-on and turn-off transitions separately, and it is suitable for working with asymmetrical supplies required by SiC MOSFETs.

With the development of silicon carbide devices, the use of low-voltage Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in series has become an option in medium/high voltage applications, but it introduces voltage imbalance problem and SiC MOSFETs suffer the great voltage peak stresses as well as the extremely high dv/dts. This brings great challenges to the insulation design of the gate driver circuit. In this study, based on the strategy of adjusting the driving signal time delay, an active gate driver is designed, it can not only reduce the design of sampling isolation through the ‘floating ground’ but also reduce the requirement for the coupling capacitance of the isolated power supply. Finally, the proposed active gate driver circuit is verified through experiments.

The trend in the development of power converters is focused on efficient systems with high power density, reliability and low cost. The challenges to cover the new power converters requirements are mainly concentered on the use of new switching-device technologies such as silicon carbide MOSFETs (SiC). SiC MOSFETs have better characteristics than their silicon counterparts; they have low conduction resistance, can work at higher switching speeds and can operate at higher temperature and voltage levels. Despite the advantages of SiC transistors, operating at high switching frequencies, with these devices, reveal new challenges. The fast switching speeds of SiC MOSFETs can cause over-voltages and over-currents that lead to electromagnetic interference (EMI) problems. For this reason, gate drivers (GD) development is a fundamental stage in SiC MOSFETs circuitry design. The reduction of the problems at high switching frequencies, thus increasing their performance, will allow to take advantage of these devices and achieve more efficient and high power density systems. This Thesis consists of a study, design and development of active gate drivers (AGDs) aimed to improve the switching performance of SiC MOSFETs applied to high-frequency power converters. Every developed stage regarding the GDs is validated through tests and experimental studies. In addition, the developed GDs are applied to converters for wireless charging systems of electric vehicle batteries. The results show the effectiveness of the proposed GDs and their viability in power converters based on SiC MOSFET devices. La tendencia en el diseño y desarrollo de convertidores de potencia está enfocada en realizar sistemas eficientes con alta densidad de potencia, fiabilidad y bajo costo. Los retos para cubrir esta tendencia están centrados principalmente en el uso de nuevas tecnologías de dispositivos de conmutación tales como, MOSFETs de carburo de silicio (SiC). Los MOSFETs de SiC presentan mejores características que sus homólogos de silicio; tienen baja resistencia de conducción, pueden trabajar a mayores velocidades de conmutación y pueden operar a mayores niveles de temperatura y tensión. A pesar de las ventajas de los transistores de SiC, existen problemas que se manifiestan cuando estos dispositivos operan a altas frecuencias de conmutación. Las rápidas velocidades de conmutación de los MOSFETs de SiC pueden provocar sobre-voltajes y sobre-corrientes que conllevan a problemas de interferencia electromagnética (EMI). Por tal motivo, el desarrollo de controladores de puertas es una etapa fundamental en los MOSFETs de SiC para eliminar los problemas a altas frecuencias de conmutación y aumentar su rendimiento. En consecuencia, aprovechar las ventajas de estos dispositivos y lograr sistemas más eficientes y con alta densidad de potencia. En esta tesis, se realiza un estudio, diseño y desarrollo de controladores activos de puerta para mejorar el rendimiento de conmutación de los MOSFETs de SiC aplicados a convertidores de potencia de alta frecuencia. Los controladores son validados a través de pruebas y estudios experimentales. Además, los controladores de puerta desarrollados son aplicados en convertidores para sistemas de carga inalámbrica de baterías de vehículos eléctricos. Los resultados muestran la importancia de los controladores de compuerta propuestos y su viabilidad en convertidores de potencia basados en carburo de silicio.

The series connection of silicon carbide (SiC) MOSFETs and the cascaded system allows operating at a higher voltage than the rated voltage of devices. However, the unbalancing voltage problem occurs in the series-connected devices. The main reason for the unbalancing voltage problem is the parasitic capacitance of the device's gate to the ground. There are several methods for balancing the series-connected device voltage. The snubber circuits, active clamp circuits and the active gate driver. In this paper, the active gate driver method is proposed to control the unbalanced device voltage. Also, the device voltage sensing circuit and the feedback controller are designed in detail. Finally, the proposed active gate driver is verified with the simulation.

This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high dv/dt of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the dv/dt with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the dv/dt sequence of the switching transients. Hence, the dv/dt and di/dt can be actively controlled separately, and the tradeoff between the dv/dt and EON switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for dv/dt active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak dv/dt from -175 to -120 V/ns for the 400 V application.

As power devices are series connected for voltage sharing, loss of gate drive synchronization and/or variation in device switching time constant can cause voltage imbalance. Capacitors (in snubbers) are usually added to maintain series voltage balance, however, in snubberless designs, where active gate drivers are used for voltage balancing during transients, it is necessary to evaluate the limits of the power device under transient unsynchronized switching. In series devices, desynchronization of the gate drivers in series connected devices will cause the faster switching device into avalanche during turn-OFF. Power device failure from BJT latch-up in MOSFETs and thyristor latch-up in IGBTs can result in potentially destructive consequences for the entire converter. Failure of the power device under avalanche is exacerbated by the (i) device commutation rate (ii) device junction temperature (iii) magnitude of gate drive switching mismatch and (iv) ratio of the DC bus voltage to intrinsic breakdown voltage of the device. This paper uses experimental measurements and finite element models to investigate the limits of power device failure under transient unsynchronized switching of series connected SiC trench MOSFET and silicon IGBT devices.

High power insulated gate bipolar transistors (IGBTs) are integral to modern power conversion systems across railway traction, renewable energy, and HVDC transmission. Traditional gate drivers offer limited adaptability under dynamic conditions, leading to increased switching losses and reduced reliability. This paper proposes a novel current source based active gate driver (CS-AGD) tailored for high-power IGBT modules, enabling dynamic control of transient switching characteristics. We design and prototype a CS-AGD circuit, integrate it within a wide-range double-pulse test platform, and experimentally validate its performance under voltages up to 1000 V and currents up to 600 A. Results demonstrate significant reductions in switching losses and peak voltage/current overshoots compared to conventional gate driving strategies. The proposed solution offers enhanced controllability, opening new pathways for reliability- optimized and high-efficiency power electronic systems.

Silicon carbide (SiC) devices have the benefit of low energy losses and high operation temperature. The fast switching speed of SiC may result in serious electromagnetic interference (EMI) noise, overshoot voltage, and even false triggering. To address these issues, an intelligent cascaded multi-level active gate driver (AGD) topology is proposed to control the switching trajectory of the power device dynamically. It can flexibly adjust the switching speed by either speeding up or slowing down. Its slow turn-off mode has the advantage of short turn-off delay compared with a two-stage turn-off. The circuit has the benefits of simple-realization and cost-effectiveness. Also, a switching behavior trajectory-based model predictive control (MPC) strategy is introduced for this gate driver circuitry. The MPC strategy balances the switching energy losses, EMI noise, and switching process duration. The experimental results reveal that the proposed intelligent AGD can provide desirable performance for controlling the slew rate of the semiconductor device

When it comes to power systems, both overall performance and efficiency are key factors in the design of the power device drivers. Using multi-level power gating logic, this study developed an active gate driver (AGD) design that is capable of driving the power transistor at different voltage levels. To lessen the amount of power that the AGD consumes, it is equipped with an effective power gating control logic. Additionally, the Four-stage Stability Control Circuit inside of the AGD makes certain that each and every power MOS device contained within the buffer arrays of the Output Stage is equally utilized. For the implementation of the AGD design, the TSMC 180-nm High-voltage (HV) Bipolar-CMOS-DMOS (BCD) process was utilized. The measurement outcomes with [Formula: see text] equal to 2[Formula: see text]nF and an operating PWM frequency of 400[Formula: see text]kHz validate the functionality of the AGD design. It dissipates an average of 533[Formula: see text]mW, which is a combination of static and dynamic power. Finally, the power gating mechanism offers a power reduction of 49.23%, as determined by a comparison of two cycles with and without power gating circuit installed.

Silicon carbide (SiC) MOSFET features low switching loss and it is advantageous in high switching frequency application, but the manufacture per Ampere cost is approximately five times higher than the silicon (Si) IGBT. Therefore, by paralleling Si IGBT and SiC MOSFET together, a trade-off between cost and loss is achieved. In this paper, a four control freedoms active gate driver (AGD) including turn-on delay, turn-off delay, and two independent gate voltages, is proposed to optimize the performance of the paralleled device. By adjusting these four control freedoms, optimal operation for paralleled device can be obtained. Moreover, the proposed AGD can dynamically adjust the current ratio between two paralleled devices, which can help achieve thermal balance between two devices and improve system reliability. Double pulse test (DPT) experimental results are presented and analyzed to validate the effectiveness of the proposed AGD for paralleled Si IGBT and SiC MOSFET application.

Featuring higher switching speed and lower losses, the silicon carbide MOSFETs (SiC MOSFETs) are widely used in higher power density and higher efficiency power electronic applications as a new solution. Due to the limited current capability of a single module, more modules parallel-connected are necessary for higher power application. However, current sharing is the key obstacle. In this article, an active gate driver (AGD) for high-power SiC MOSFETs is presented to balance the currents of parallel-connected SiC MOSFET modules. The principle of the AGD is based on dynamic gate drive voltage adjustment to synchronize current edges and current slopes among parallel-connected SiC MOSFET modules automatically. Each AGD measures and controls the current of its SiC MOSFET module individually. No extra supervising control circuit is needed. In addition, the hardware and software configurations are independent of the system design and no restrictions on the number of SiC MOSFET modules connected in parallel exist. Finally, the switching performance of the AGD was experimentally verified on two parallel-connected SiC MOSFET modules in a multipulse test under constant and variable load currents. In addition, the effectiveness of AGD under different control topologies has been studied with simulation and verified using three parallel-connected SiC MOSFET modules.

Flyback converters with synchronous rectifiers are an important topic in power electronics, given their widespread use in various applications and the focus on efficiency improvement. However, flyback converters suffer from a high overvoltage across the synchronous rectifier on their secondary side. This overshoot voltage is a result of resonance between the flyback transformer stray inductance and the output capacitance of the rectifier. This paper presents an in-depth experimental study on the optimization of dead time and Active Gate Driving in flyback converters employing synchronous rectifiers, i.e. Silicon Carbide Power MOSFETs in place of the secondary rectifier driven synchronously with the primary switch. The focus is the influence of symmetrical dead time variation between the primary and secondary switches on switching losses and overshoot voltage. In addition, the influence of a three voltage level active gate driver on the overshoot voltage and switching losses is examined, finding no significant influence. The findings from this study contribute to the existing body of knowledge by providing a nuanced understanding of dead time optimization in flyback converters with synchronous rectifiers, as well as the utilization of Active Gate Drivers in such systems. The results have implications for the design and operation of these converters, potentially leading to more efficient and reliable systems.