A Very Efficient Redundancy Analysis Method Using Fault Grouping

With the development of memory density, the probability of occurring faults in memory also increases. To overcome this problem, many built-in redundancy analysis (BIRA) algorithms have been proposed to repair the faults using redundancy cells in memory. Most of previous algorithms have focused on single memory block with local spare cell architecture. However, many memories in system consist of multiple local memory blocks with various spare cell architectures. Thus, the proposed algorithm is based on not only local spare cell but also various spare cell architectures. The experimental results show that repair rate, and hardware overhead of BIRA with various spare cell architectures in multiple memory blocks. The proposed algorithm is practical solution for multiple memory blocks which have global spare cell and common spare cell.

The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.

Advanced capacity and density of memory have resulted in an increase in the probability of memory faults. The in-memory Error Correction Code (ECC), which solves this problem, is a widely used technology to improve the yield of highly integrated memory. However, the use of in-memory ECC causes problems that have not been considered in memory repair algorithms. Redundancy analysis is effective for repairing memory with redundant memory and in-memory ECC. In this paper, an ECC-aware fast and reliable pattern matching redundancy analysis algorithm for memory using both spare memory and in-memory ECC is proposed. This algorithm simplifies large-scale fault groups using in-memory ECC and includes an early termination method that can determine whether a memory that cannot be repaired with line spares can be repaired considering in-memory ECC. Experimental results show that the proposed pattern matching redundancy analysis algorithm achieves a similar yield but 14.6% less RA time and 8.6 times higher reliability compared to the existing redundancy analysis algorithms.

A built-in self-repair (BISR) scheme for random access memories (RAMs) with 2-D redundancy has a built-in redundancy analyzer (BIRA) for allocating the redundancy. The BIRA typically has a cache-like element called local bitmap for storing the fault information temporary. In this paper, a high-repair-efficiency BISR (HRE-BISR) scheme for RAMs is proposed. The HRE-BISR reuses the local bitmap to serve as spare bits such that it can repair more faults. In addition, a row/column/bit redundancy analysis (RCB-RA) algorithm for a RAM with spare rows, spare columns, and spare bits is presented. Simulation results show that the proposed HRE-BISR scheme can provide higher repair rate (RR) than a typical BISR scheme without reusing the local bitmap as spare bits. Only about 0.44% additional hardware overhead is needed to modify the local bitmap as spare bits. In addition, the HRE-BISR scheme using $3\times 3$ -bit local bitmap for RA only incurs about 0.08-ns delay penalty for a $512\times 16\times 32$ -bit RAM with one spare row and one spare column. However, the HRE-BIRA scheme with RCB-RA algorithm can provide 0.48%–11.95% increment of RR for different fault distributions.

SIERRA—Simulation environment for memory redundancy algorithms

The purpose of this paper is to present a conceptual approach and to make practical recommendations on how to improve the current Automatic Test Equipment (ATE) testing and maintenance capabilities by utilizing the existing cloud computing model to build a globally linked ATE maintenance system. The basic tenet of the ATE community is to support a multi-tiered maintenance concept which, in general, is a three tiered system that is composed of organizational maintenance (O-level), intermediate maintenance (I-level), and depot maintenance (D-level) organizations. The goal of the ATE is to (1) quickly and accurately detect and isolate each fault, (2) provide software tools for analyzing historical data, and (3) gather, manage, and distribute accurate and reliable maintenance information for the failed Unit Under Test (UUT). The ATE system should provide services that will (1) maintain a repository of information that will improve fault detection and isolation, allow for off-platform assessments, document failures, and help quantify corrective actions, (2) reduce false UUT pulls, and (3) reduce repair time by prompting repair procedures. Furthermore, the ATE system should provide additional services that will help optimize the time to diagnose problems by using collected failure information and by recommending entry points into the Test Program Set (TPS) software. It should also present information to the ATE maintainer to aid in informed repair decisions which could be in the form of pilot debrief results, platform Built In Test (BIT) results, O-level test outcomes and corrective actions, and maintenance and usage history of the platform and UUT. So, based on this definition of ATE maintenance the use of cloud computing can be used to provide services to improve the overall ATE testing throughput which will result in bottom line improvements to ATE life cycle costs. By using cloud computing, which is defined to be “a model for enabling ubiquitous, convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction”, users can develop cloud computing models that will provide access to application software and databases that can be used to build a globally linked ATE maintenance system. This paper will discuss the essential characteristics of the cloud computing models and define the various flavors of cloud offerings available to designers today. This paper will also analyze the cloud computing model to arrive at a conceptual approach that can be used to enhance the current ATE Testing and Maintenance capabilities. Practical recommendations will be discussed on how to transform the current ATE Testing and Maintenance capabilities into the specific cloud computing model offerings in order to help configure a globally linked ATE maintenance system.

Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. For example, the ratio of the redundancy analysis time to the test time for a 512 Kbit RAM tested by a March-14 test with solid data backgrounds is only about 0.25%. On the other hand, the proposed fusing scheme can achieve about 86.94% reduction of repair setup time in comparison with a typical fusing scheme for 20 512 × 16 × 64-bit RAMs of which each RAM has one spare row and one spare column.

One of the important steps that a semiconductor chip goes through is electrical testing, which typically is performed on an automated test equipment (ATE) platform. The primary goal of this step is to achieve maximum test coverage while minimizing testing time as much as optimal. There are various test methods used in testing, ranging from a simple continuity test to implementations such as built-in self-tests (BISTs) in which the chip is instructed to run internally and the test program checks for the result only when it is done. BISTs are, in a way, non-deterministic in nature; testing time can vary depending on the internal clock frequency at which the test is run and other factors based on the chip's operation. One way to optimize testing time of non-deterministic tests at ATE is to read the results register immediately on completion of the BIST execution, and not wait for a hard-coded amount of time to elapse - typically, an amount of time based on the slowest possible test execution to complete. This paper discusses a method that eliminates unnecessary time lost waiting for data that may have long arrived.

In this paper, an experimental analysis and study of the Modified Signed-Digit (MSD) method was conducted, which aims to hide a quantity of secret data represented in a grayscale image of size 512 × 512 in a set of cover images. Some quality metrics such as signal-to-noise ratio (PSNR), mean squared error (MSE), and embedding capacity (BPP) were measured. As well as calculating, the optimal number of cover images, the time taken in the hiding process, and the consumed memory. The experiments were conducted two different sizes of cover images, where the number of cover images required for the secret image is determined according to some inputs such as the number of pixels n in each group of the cover image and the number of bits in each block of the secret image L=n+1. Also, four different values of n, (2, 3, 4, 5). We tried to find the best value for the number of bits in each block L of the secret image and in each case of n to achieve the best case for image quality PSNR, MSE for both cover image sizes, and on the other hand, less time memory consumption. By using the Matlab program, we compared the results at different cover image sizes, we found that as the larger size used, the fewer cover images are needed and less time consumption. On the other hand, more memory consumption. For the other metrics, PSNR, MSE and BPP, close results were obtained. Finally, the best choice remains related to the user and the type of application or the required performance, whether in image quality or in less memory and time consumption with a larger embedding capacity. Keywords: MSD algorithm, Signal-to-noise ratio (PSNR), Mean square error (MSE), Bit-per-pixel (BPP), Memory consumption, Time consumption.

As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.

Integrated circuit (IC) applications have become viable, reliable, and cheaper with deep-submicron technologies in VLSI industry. SoC (system on chip) is a microchip, which holds the necessary hardware and software to implement various functions onto a single chip. An IC should be tested during design process to check the correctness of the design and also to check the functionality of the design after fabrication. Testing cost shares almost half of the manufacturing expenditure. Achieving high-test quality in reduced VLSI geometry increases the complexity of the testing methods because of huge volume of test data. Automatic testing equipment (ATE) reduces testing efforts, but it has limited memory in comparison with the huge volume of the test data. One of the methods to reduce the burden of ATE is test data compression. The advantages of test data compression are as follows: (i) reduction in memory requirement for ATE and (ii) reduction in testing time. Though many advanced algorithms are used for testing of VLSI circuits, most of them are expensive in terms of test data volume and power. This survey discusses all the test data compression methods, and it helps the researchers in testing domain.

System testing is one of the test stages of a software test, making sure that the software intended for the system is working as it should be. This study has aimed to automate the manual system testing of the Field Programmable Gate Array (FPGA) -based ADC reference design boards together with its corresponding software. Test scripts were developed for the automation of two ADC boards which was tested to five different versions of Linux image and boot files. Both were executed on the manual system test setup and automated system test set up and the test time and parameter result were recorded. The study was able to show that the test execution time of the automated system test is significantly faster compared to the manual system test without compromising the accuracy of the measured parameters.

Green energy sources such as solar power, wind, and biomass ... are getting more attention especially after the nuclear crisis caused by earthquake in Mar. 2011 in Japan. The solar power has been considered to be the major contributor of the green energy. There are more than enough solar irradiations available to satisfy the world's energy demands. However the traditional photovoltaic (PV) systems suffer from various power losses, the performance shows average losses of about 20%-30% in electricity production. Some companies provide advance system architectures which can boost solar panel output power by up to 20%-25%. One of a key element of the system is the DC-DC converter [1]. Texas Instruments' high voltage gate driver ICs (HVIC) can be used as a DC-DC converter, half/full bridge applications or class-D audio amplifiers. There are challenges for the HVIC testing. First, the timing measurements for propagation delay matching in both buck and boost which need to be in nanoseconds range but the typical production automatic test equipment (ATE) specification of timing measurement unit (TMU) accuracy is approximate 2 nanoseconds (ns) and meanwhile, the output voltage of gate driver application can exceed 100 volts. Second, test time and multi-site testing have to be considered. In this paper, we have discussed the critical timing measurements and have successfully implemented the multi-site delay matching testing on IFLEXTM ATE platform with 100 picoseconds (ps) resolution while the boost is operating at 120V.

Network-on-chip (NoC) has been proposed as a scalable communication infrastructure to establish connections between integrated cores which are increased on a single chip. NoC structure consisting of components and elements such as routers, processing elements and links that can be error prone. Therefore, to achieve the correct functioning of a network, test operation has been a major concern for chip designers. In offline test mechanism, the distance between test pattern generator and destinations has significant impact on the test time. Using multicast scheme, this paper proposed a new mechanism that tests all cores. Our proposed approach first divides the network to four parts and then locates one ATE with four ports in the middle of the network. Based on our method, test operations are manipulated in parallel on each partition, individually. A new method is proposed that distributes test packets and collects test responses, simultaneously. Simulation results were also compared with some prior works by means of the proposed mechanism indicating that delivering test packets’ latency was decreased about 63% and the total number of hop counts to reach the specified destination was declined approximately 34%.

The portable intelligent troubleshooter (POINTER) system, originally developed for manual fault isolation, has been applied to intelligent automatic testing, which requires a fresh look at test program set (TPS) design from the perspective of testability theory and artificial intelligence. The resulting novel automatic test and diagnostic approach is a significant departure from conventional test programming techniques. A prototype automatic test equipment (ATE) system that implements a diagnostic control algorithm that computes a context-sensitive test strategy in real time has been developed. This control algorithm operates on a dependency model that describes the testability characteristics of the unit under test (UUT) and a test procedures file that contains the instrumentation setup for each test available for the UUT. This approach to automated diagnostics reduces time and costs in UUT repair. >