Failure bitmap compression method for 3D-IC redundancy analysis

The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.

In recent years, many built-in self-test techniques have been proposed based on feedback shift-registers for pattern generation and signature analysis. But in general, these test-registers cannot test several modules of the chip concurrently, and they have to be controlled by external automatic test equipment. The authors propose a method to integrate additional test-control logic into the chip. On the basis of a register-transfer description of the circuit, the test control is derived, and a corresponding finite automation is synthesized. A hardware implementation is proposed, resulting in circuits where the entire self-test only consists in activating the test mode and clocking and evaluating the overall signature. >

Test cost and yield enhancements are the vital parameters as the memory capacity and density increase. Built-in redundancy analysis (BIRA) is primarily used for incorporated memories to resolve yield and quality by replacing faulty cells with available cells. Various BIRA approaches need different area overheads to achieve optimal repairs. It is not easy to get low area overhead along with optimal repair rate. A novel BIRA method is proposed that requires less storage for storing faulty address information by deleting the data of unimportant faulty cell addresses. The proposed BIRA examines redundant spares quickly to achieve optimal repair rate. Simulation results show that the proposed BIRA does the spare allocations efficiently.

With the growth of memory capacity and density, test cost and yield improvement are becoming more important. In the case of embedded memories for systems-on-a-chip (SOC), built-in redundancy analysis (BIRA) is widely used as a solution to solve quality and yield issues by replacing faulty cells with extra good cells. However, previous BIRA approaches focused mainly on embedded memories rather than commodity memories. Many BIRA approaches require extra hardware overhead to achieve the optimal repair rate, which means that 100% of solution detection is guaranteed for intrinsically repairable dies, or they suffer a loss of repair rate to minimize the hardware overhead. In order to achieve both low area overhead and optimal repair rate, a novel BIRA approach is proposed and it builds a line-based searching tree. The proposed BIRA minimizes the storage capacity requirements to store faulty address information by dropping all unnecessary faulty addresses for inherently repairable die. The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. Experimental results show that the proposed BIRA achieves optimal repair rate, fast analysis speed, and nearly optimal repair solutions with a relatively small area overhead.

최근의 시스템 온 칩 (SoC) 설계 기술의 발전에 따라, 수백개의 임베디드 메모리 코어들이 칩의 대부분의 면적을 차지하고 있다. 그러므로 시스템 온 칩의 수율은 임베디드 메모리 코어들의 수율에 따라 결정된다고 볼 수 있다. 최적의 수리 효율을 가지는 built-in self repair (BISR)을 모든 메모리들이 가지고 있게 된다면 면적의 부담이 너무 크다. 본 논문에서는 이와 같은 면적의 부담을 줄이기 위하여 메모리들을 그룹화 한 후에 비트맵 메모리를 공유하여 면적 부담을 크게 줄이는 방법을 제안한다. 제안하는 비트맵 메모리 공유방법은 built-in redundancy analysis (BIRA)의 면적을 크게 줄일 수 있다. 실험결과를 통해서 보면 제안하는 방법이 면적 부담을 대략 80%정도 줄이는 것을 확인 할 수 있다.

This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform matches with the one on the customer's operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer's operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.

To increase device memory yield, many manufacturers use incorporated redundancy to replace faulty cells. In this redundancy technology, the implementation of an effective redundancy analysis (RA) algorithm is essential. Various RA algorithms have been developed to repair faults in memory. However, nearly all of these RA algorithms have low analysis speeds. The more densely compacted the memory is, the more testing and repair time is needed. Even if the analysis speed is very high, the RA algorithm would be useless if it did not have a normalized repair rate of 100%. In addition, when the number of added spares is increased in the memory, then the memory space that must be searched with the RA algorithms can exceed the memory space within the automatic test equipment. A very efficient RA algorithm using simple calculations is proposed in this work so as to minimize both the repair time and memory consumption. In addition, the proposed algorithm generates an optimal solution using a tree-based algorithm in each fault group. Our experiment results show that the proposed RA algorithm is very efficient in terms of speed and repair.

With advancements in manufacturing and design technology, memory integration density has improved. However, as integration density increases, the cost of testing and repairing memory has also risen, posing a significant challenge in memory production. To address this challenge, built-in self-repair (BISR) has been proposed. Traditional built-in redundancy analysis (BIRAs) performs limited analysis of faults during the fault collection process, resulting in a significant delay in generating a repair solution after the test sequence is completed. This inefficiency arises from the time required to repair the memory posttest. This article proposes a new fast and optimal BIRA using smart potential case collection. The proposed BIRA conducts a detailed analysis of detected faults during the test process. Using this novel fault collection results, a potential case is generated. This is a repair case that can repair the memory with a high probability and is generated immediately after the test sequence ends. If the memory cannot be repaired by the potential case, an exhaustive search is conducted for the faults requiring further analysis to generate an optimal repair solution. Compared to previous studies, the proposed BIRA demonstrates extremely low analysis time with an optimal repair rate.

Machine repairing systems with standby switching failure

In this paper, we present an analysis of a machine repair problem with M operating machines and S standbys, in which c repairmen are responsible for supervising these machines and follow a multi-threshold, synchronous vacation policy. With such a policy, at a repair completion instant, if the number of the failed machines in the system is less than a preset threshold value, partial idle servers together take a single vacation (or leave for a random amount of time doing other secondary job). At the end of a vacation, they return to repair the failed machines (or waits for the arrival). The steady-state probabilities are solved by using the matrix-analytic method, and formulae of system performance measures are thereby obtained. A cost model is then developed to formulate an optimization problem to find the minimum cost. The direct search and quasi-Newton methods are implemented to determine the optimal number of servers, the optimal threshold policy and the optimal repair rate.

This paper introduces a digital method for the evaluation of SSB (Single SideBand) phase noise of analog/RF signals. The technique is based on 1-bit signal acquisition with a digital Automated Test Equipment (ATE) and a dedicated postprocessing algorithm that permits to reconstruct the timedomain phase fluctuations of the analog/RF signal from the captured binary vector. SSB phase noise is then obtained by applying an FFT on the reconstructed signal corresponding to phase fluctuations. The proposed method is validated through simulation and results demonstrate an excellent agreement with SSB phase noise obtained using conventional analog method. The proposed method therefore permits to achieve low-cost evaluation of phase noise frequency-domain characteristics for analog/RF signals.

Locating the scan chain faults is very important for dedicated IC manufacturers to guide the failure analysis process for yield improvement. In this paper, we propose a new symbolic simulation based scan chain diagnosis method to solve the scan chain diagnosis resolution problem as well as the multiple faults problem. The proposed method uses a new symbolic simulation with the faulty probabilities of a set of candidate faulty scan cells in a bounded range and to analyze the effects caused by faulty scan cells in good scan chains. In addition, we use the faulty information in good scan chains that are not contaminated by the faults while unloading scan out responses. In addition, a new score matching method is proposed to effectively handle multiple faults and to improve the diagnostic resolution by ranking the candidate scan cells in the candidate list. Experimental results demonstrate the effectiveness of the proposed method.

An extended redundancy analysis and its applications to two practical examples

<p>Declines in global marine finfish catches, which accounts for ~15% of the animal protein consumed by humans, has caused a 6-fold increase in total reported catch of invertebrates since 1950. This has led to the over-exploitation and decline of many marine invertebrate fisheries. The red rock lobster (Jasus edwardsii) fishery is New Zealand’s most economically valuable inshore fishery. The current management strategy relies on the assumption that the stock is comprised of a single panmictic population. However, more recent studies have challenged the genetic homogeneity of Jasus edwardsii across the Tasman sea and described high levels of self-recruitment in a Stewart Island subpopulation. A disregard for the underlying genetic structure in the management of a fishery can lead to excessive removal of individuals from populations contributing to the overall genetic diversity of the stock and thus reduce the species adaptability. The ability to adapt to new environments is particularly important in the context of global climate change and can significantly affect the long-term sustainability of the stock. Thus, the goal of this study was to identify specific patterns of genetic diversity of Jasus edwardsii population and provide an interpretation and assessment of the impact on the NZ fishery. The first objective was to optimize and validate molecular and bioinformatic protocols of Single Nucleotide Polymorphism (SNP) discovery for the red rock lobster Jasus edwardsii. The double digest restriction-site associated DNA (ddRADseq) protocol was optimized for the relatively large red rock lobster genome, which also has a high paralog content. The impact of bioinformatic processing on the population genetic inferences was then assessed by testing three different SNP discovery pipelines with the Rad-loci pipeline producing the most optimal marker discovery rate with a low level of missing data and a low SNP error rate. An analysis of technical replicates confirmed the reproducibility of both the molecular and bioinformatic protocols and also the validated the data generation process suitable for population genetic analyses. The second objective of my thesis was to investigate the genetic structure and population connectivity of adult red rock lobsters. The SNPs discovered were characterised as selectively neutral or under divergent selection (outlier) and both types of markers were analysed using Bayesian model-based clustering (STRUCTURE), non model-based multivariate analysis (Discriminant Analysis of Principal Components (DAPC)) and F-statistics. A lack of population differentiation using neutral genetic markers indicated a high level of gene flow and connectivity between populations. In contrast, there was evidence for selective pressure as a result of the analysis of outlier markers. Three main regions were identified: North-East NZ, North-West NZ and South NZ sub-populations, as part of a larger NZ metapopulation (FST ranged from 0.025 to 0.049, P < 0.001). The results of this study suggested that high levels of gene flow and connectivity are counteracted to some extent by the local selection that promotes the survival and reproduction of locally adapted genotypes. However, the strength of this selective pressure still permits low levels of survival and reproduction of non-optimal genotypes causing allele frequency homogenisation of the new generation of lobsters. The third objective was to investigate the levels of connectivity and adaptive divergence of the red rock lobster pueruli/juvenile lobsters for comparison with pattern of divergence of adult lobster in order to investigate the mechanisms of population structure formation. A suite of Bayesian clustering, non-model multivariate analysis and F-statistics were employed in the assessment of neutral and outlier markers developed for pueruli/juveniles. Similar to adult lobsters, pueruli/juveniles were characterised by a low level of divergence of the neutral markers indicating effective larvae dispersal. Outlier markers detected population differentiation patterns likely to originate from a phenotype – environment mismatch resulting in post-settlement mortality of non-adapted genotypes. The similarity between patterns of genetic divergence of adult lobsters and late juvenile/early juveniles indicates that post-settlement mortality, driven by local environmental conditions, has most likely occurred on earlier developmental stages of Jasus edwardsii, which were not possible to sample in my study. The final objective was to explore environment–genotype associations of Jasus edwardsii. Biological Environment Stepwise (BEST) analyses, redundancy analyses (RDA) and generalized linear modelling (GLM) consistently indicated a correlation between the annual amplitude of sea surface temperature (SST) and adaptive population divergence. In addition, an influence of spatial distribution on the patterns of adaptive population differentiation was also detected via RDA. From these results I propose a mechanism underlying the patterns of population differentiation discovered in Chapters 3 and 4: a latitudinal gradient of SST appears to be the selective force promoting the adaptive divergence of the lobster populations with local patterns of connectivity distorting the gradient and thus forming three distinct temperature adapted genotypes (North-West, North-East, and South). An environmental association analysis offered 43 candidate loci, which after alignment of transcriptome-mapped reference catalog sequences to annotated protein databases identified a candidate gene for thermal adaptation - UDP-glycosyltransferase (UGT). UGT is a detoxification enzyme involved in the metabolization of a variety of endogenous and environmental compounds and its activity and gene expression patterns have been linked to temperature. This study provides evidence for the local adaptations of the NZ population of Jasus edwardsii to SST, which together with the efficient mechanism of larval dispersal creates a system likely resilient to changes in temperature. This feature is important in the light of climate change-induced range shifts and supports the long-term sustainability of the red rock lobster fishery. The three genetically distinct regions identified coincide with existing boundaries of the management units and therefore do not require an adjustment of the current management regime.</p>

As advances in memory density and capacity result in an increase in the probability of fault occurrence, many studies on built-in redundancy analysis (BIRA) have been conducted to address this problem. However, conventional BIRAs cannot directly find a final repair solution as soon as test sequences of the built-in self-test (BIST) are over, because they require starting the fault analyses after finishing the test sequences to achieve an optimal repair rate. For this reason, additional analysis time is inevitable, which affects total test costs. In this paper, a dynamic BIRA is proposed for memory repair. It can find a final repair solution directly as soon as test sequences if the BIST are over and achieve an optimal repair rate. The proposed BIRA can restore faults in fault-storing content-addressable memories whenever the spaces in them can be reduced via dynamic fault analysis. Furthermore, the proposed BIRA can be implemented with a reasonable hardware size. This is demonstrated via experiments.