Adaptive packet processing on CPU-GPU heterogeneous platforms

The complexity of modern embedded systems is ever increasing and the selection of target platforms is shifting from homogeneous to more heterogeneous and powerful configurations. In our previous works, we exploited the power of model-driven techniques to deal with such complexity by enabling the automatic generation of full-fledged functional code from UML models enriched with ALF action code. Nevertheless, the scope was bounded to CPU-based platforms. In this work we propose a preliminary definition of the means to build upon the current code generator to enable the generation of code targeting heterogeneous platforms, more specifically conceiving mixed CPU-GPU configurations. The aim is to minimise the effort of the user in modelling platform-related information by embedding the greatest feasible amount of it into the transformation process.

Heterogeneous computing platforms with multicore central processing units (CPUs) and graphics processing units (GPUs) are of increasing interest to designers of embedded signal processing systems since they offer the potential for significant performance boost while maintaining the flexibility of software-based design flows. Developing optimized implementations for CPU-GPU platforms is challenging due to complex, inter-related design issues, including task scheduling, interprocessor communication, memory management, and modeling and exploitation of different forms of parallelism. In this paper, we present an automated, dataflow based, design framework called DIF-GPU for application mapping and software synthesis on heterogeneous CPU-GPU platforms. DIF-GPU is based on novel extensions to the dataflow interchange format (DIF) package, which is a software environment for developing and experimenting with dataflow-based design methods and synthesis techniques for embedded signal processing systems. DIF-GPU exploits multiple forms of parallelism by deeply incorporating efficient vectorization and scheduling techniques for synchronous dataflow specifications, and incorporating techniques for streamlining interprocessor communication. DIF-GPU also provides software synthesis capabilities to help accelerate the process of moving from high-level application models to optimized implementations.

High performance computing of stiff bubble collapse on CPU-GPU heterogeneous platform

Given the problems of high energy consumption and unreasonable resource utilization in current heterogeneous cloud computing platforms, this paper proposes an energy-efficient task scheduling strategy. First, by analyzing the relationship between the energy consumption of physical machines and the utilization rate of CPU-GPU resources, we can establish the task scheduling model and energy consumption model. Second, a task scheduling method HCGTS (Heterogeneous CPU-GPU Task Scheduling) for energy consumption optimization of CPU-GPU heterogeneous cloud platform is proposed. Different from traditional subtasks, we divide the multi-task data flows into CPU tasks, GPU tasks and pending tasks, which are scheduled and executed by different processors to implement multi-task parallel scheduling. In addition, the execution order of subtasks is dynamically adjusted to realize the load balance of CPU and GPU, thereby reducing the task completion time and overall energy consumption. Finally, the simulation experiment is completed on the cloud simulation software. Through comparing with the other three algorithms, the HCGTS algorithm has better performance in terms of execution time, resource utilization and energy consumption optimization.

Heterogeneous multi-core platforms that contain different types of cores, organized as clusters, are emerging, e.g., ARM’s big.LITTLE architecture. These platforms often need to deal with multiple applications, having different performance requirements, executing concurrently. This leads to the generation of varying and mixed workloads (e.g., compute and memory intensive) due to resource sharing. Run-time management is required for adapting to such performance requirements and workload variabilities and to achieve energy efficiency. Moreover, the management becomes challenging when the applications are multi-threaded and the heterogeneity needs to be exploited. The existing run-time management approaches do not efficiently exploit cores situated in different clusters simultaneously (referred to as inter-cluster exploitation) and DVFS potential of cores, which is the aim of this paper. Such exploitation might help to satisfy the performance requirement while achieving energy savings at the same time. Therefore, in this paper, we propose a run-time management approach that first selects thread-to-core mapping based on the performance requirements and resource availability. Then, it applies online adaptation by adjusting the voltage-frequency ( V-f ) levels to achieve energy optimization, without trading-off application performance. For thread-to-core mapping, offline profiled results are used, which contain performance and energy characteristics of applications when executed on the heterogeneous platform by using different types of cores in various possible combinations. For an application, thread-to-core mapping process defines the number of used cores and their type, which are situated in different clusters. The online adaptation process classifies the inherent workload characteristics of concurrently executing applications, incurring a lower overhead than existing learning-based approaches as demonstrated in this paper. The classification of workload is performed using the metric Memory Reads Per Instruction (MRPI). The adaptation process pro-actively selects an appropriate V-f pair for a predicted workload. Subsequently, it monitors the workload prediction error and performance loss, quantified by instructions per second (IPS), and adjusts the chosen V-f to compensate. We validate the proposed run-time management approach on a hardware platform, the Odroid-XU3, with various combinations of multi-threaded applications from PARSEC and SPLASH benchmarks. Results show an average improvement in energy efficiency up to 33 percent compared to existing approaches while meeting the performance requirements.

Fast and customizable programmable data planes (PDPs) implementing new services such as multi-flow synchronization, on- and in-time delivery, and in-network caching and compression are key enablers to future applications (e.g., streamed holograms, telesurgery, and autonomous industrial systems). This paper outlines the design principles of EP4, an application-aware extended P4-based network architecture that offers hosted applications an extensible catalog of services through its control plane. The latter configures a PDP that can achieve minimal parsing and processing for fast-tracked packets as well as customized processing and forwarding for other packets. An extended parser (eParser) performs the first task, which reduces the necessary latency experienced by packets. Alternatively, adaptive processing is achieved using an enhanced processor (eProcessor) that optionally parses customized headers using just-in-time programmable parsers. It then executes selected P4 packet processing pipelines implementing different services. These programs are installed at runtime without impacting other switch functionalities. Experimental results demonstrate the architecture’s enhanced performance compared to current solutions.

In recent years, GPU has become an important component of the system by accelerating applications with data parallelism. While traditional discrete GPU cooperates with CPU over I/O bus, more recent processor design trends feature fine-grained synchronization and inexpensive data sharing between CPU and GPU processors by tightly coupling them at a cache level. However, designing algorithms that effectively exploit these new architectural features has proved challenging. In this paper we present a novel parallel algorithm called Parafill that identifies connected regions of arbitrary topolo-gies in an image very efficiently on CPU -GPU heterogeneous platforms. Parafill is a greedy algorithm using dynamic programming memoization techniques. Essential to its efficiency is a data structure called the workload manager, which dynamically manages the complexity of work in each pass. We evaluate the performance of Parafill across two different heterogeneous platforms: a traditional discrete GPU system where the CPU and GPU are connected through I/O bus, and a single-chip processor where the CPU and GPU are tightly coupled at a cache level. We also compare Parafill to a CPU-optimized connected region algorithm using applications with different parallelism to quantify its scalability. Our experimental results show that minimizing GPU overhead and managing pass-by-pass workload are especially important for sparsely parallel applications. Tightly coupled GPUs, although less powerful than discrete GPUs, com-pete well in sparsely parallel applications because of their reduced overhead. Finally, we present two applications of Parafill: traditional flood filling and the absorption of unconnected interior regions into a containing connected region.