Adiabatic Logic Technique with Lower Power for Logic Circuits

In digital circuits, shift registers are used as the basic memory units. This paper presents a low power adiabatic Universal Shift Register, which can perform both serial and parallel shift operations. Since power dissipation is a critical factor many low power dissipation techniques have been proposed but most of these techniques have some trade-offs. Adiabatic logic technique as compared to that of a conventional CMOS technique shows promising results. A type of adiabatic technique, DFAL (Diode Free Adiabatic Logic), has been studied in this paper and NOR gate, NAND gate, XOR gate, D Flip-Flop and Universal Shift Register have been designed using this configuration. DFAL circuits are analyzed based on transistor count, power dissipation and delay. All the circuits are simulated in Pyxis (Mentor Graphics) 180nm technology at 1.8V.

Robust PID control of quadrotors with power reduction analysis

With the increasing growth of VLSI technologies the number of gates per chip is constantly increasing, as a result power dissipation increases and heat removal becomes complex and expensive. Therefore, power dissipation is one of the critical issue in low power circuits in VLSI design. Adiabatic logic is a promising technique used in low power VLSI circuits to achieve high level of performance with limiting power consumption. In Adiabatic logic, power consumption /dissipation occurring at the time of switching event is avoidable as the power supply retrieve the charge from node capacitance without heat generation which is contradict to conventional CMOS logic style and also power saving more than 50% is achievable in case of partial adiabatic circuits when compared to conventional CMOS circuits but with increase in circuit complexity. The simulation is carried out for half adder and half subtractor using 180nm CMOS technology in Cadence Virtuoso environment. From the obtained results, it is found that average power saving is more for half adder and half subtractor implemented using PFAL technique when compared to other techniques of partial adiabatic logic including conventional CMOS logic.

Spin Torque Transfer RAM (STT-RAM), a assuring possible choice of Static RAM for diminishing leakage power utilization. STT-RAM has the resistance of the MTJ (Magnetic Tunnel Junction) that changes based on stored data. By using differential sensing with reconfigurable cache cell, the STT-RAM performance can be improved. This scheme largely reduces the read disturbance error and average power dissipation with small reading current. Furthermore reducing the power dissipation of STT-RAM, we introduce one new approach as Adiabatic (Energy recovery) Technique. Adiabatic Technique main motive is to reduce the average power dissipation with no performance degradation. The Adiabatic logic and memory are attractive solution for low power application.

Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs

In the present scenario, power consumption is a vital issue in low power circuit design. The adiabatic logic and the conventional CMOS logic styles are widely used in low power VLSI design. The power saving is more effective in adiabatic circuit compared to conventional CMOS logic. In compared to gate diffusion technique, an adiabatic logic required more number of transistors, and more power is needed. The objective of this paper is to design and implement of 4:1 multiplexer using different adiabatic logic styles and gate diffusion technique and compares them in terms of the power dissipation and transistor count. The simulation has been done by using the EDA Tanner tools.KeywordsAdiabatic logicECRLPFAL2N-2N2PAdiabatic array logicPCRLGDIPower dissipationTransistor count

The energy consumption issue is efficiently addressed by adiabatic switching technique in design of low power digital circuits. Adiabatic switching technique offers the reducing in energy dissipation during switching events and recycling the load capacitance energy instead of dissipated as heat. But adiabatic circuits highly depend upon power clock and parameter variations. With the help of clocking rule, the digital circuits such as inverter and inverter chain are designed for adiabatic techniques, 2N-2N2P, Efficient Charge Recovery Logic (ECRL), Positive Feedback Adiabatic Logic (PFAL) and Clocked Adiabatic Logic (CAL) using TSPICE simulation. The results show high energy savings as compared to CMOS circuits in specified frequency range.

Non-military/noncomputer electronics industry segments such as PC's, workstations, portable electronics, the automotive and medical industries, automated test equipment, and high-end consumer goods, are evolving rapidly. They demand higher complexity and higher performance circuits and components. At the same time, many of these industry segments are being driven to shrink size, weight, and power dissipation. Standard low cost packaging approaches such as thru-hole PCB and chip and wire hybrids, can no longer efficiently interconnect these more complex circuits. These industry segments are being forced to turn to new higher performance packaging approaches such as SMT, MCM, and COB. This paper describes an innovative embedded chip MCM technology that eliminates high cost structures, as well as materials and processes in current thin film MCM technologies. A plastic encapsulated multichip technology has been developed in which an epoxy encapsulant is molded around bare die to form the MCM substrate. This new MCM process readily scales-up to high volume production and is inherently high yielding, while maintaining all of the performance advantages of the GE developed overlay HDI process. This paper describes the thermal, mechanical, and chemical stability issues that drove this development, the process used to fabricate the modules, and the cost and yield advantages associated with this structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Compared with semiconductors, SFQ logic is very fast and dissipates extremely low power. But it does not approach the theoretical power dissipation associated with an SFQ switching event and single gate speed in complex circuits. For large circuits and systems, e.g., petaflops computing, we must reduce on-chip dissipation, achieve faster clocked logic operation, and increase gate density. CMOS logic dissipates the energy required to switch a transistor pair and dissipates no power between switching events. We describe a new SFQ circuit concept that mimics CMOS to achieve ultra-low power dissipation and ultra-high clock rates. This results in physically compact, self-clocked, complementary logic (SCCL), in which clock distribution is frequency-independent. The basic element in this logic family is a simple two-junction comparator. Using TRW's 2 kA/cm/sup 2/ Nb design rules, we simulated basic digital components: shift register, AND, OR, and NOT at 20 GHz. We present the simulated and measured performance.

In the present scenario, designing a circuit with low power has become very important and challenging task, low power devices are the need of present electronics industries. In VLSI circuit design, power dissipation and leakage present are the critical design structures as they show anvital role in act of the battery. Power management of chip is the major challenge. Leakage power is a crucial parameter as the technology is shrinking (180 nanometer, 90 nanometer, 45 nanometer).The leakage current is increasing very fast so numerous technique has been proposed for leakage reduction in CMOS digital integrated circuit. This review paper demonstrates the various reduction showcase for CMOS integrated circuited.

The increasing market of portable electronics devices and battery powered portable electronic systems is making a pressure to the whole chip design industry to reduce the power dissipation of the electronics circuits so that battery backup can be increased. CMOS SRAM memory consumes almost 55% power of the total digital circuit. It is also said that memories are the power hungry devices in any digital system but today no digital system can be completed without memories. This article is based on the motivation of reduction of the dynamic power in SRAM memory and focuses on the analysis in terms of power dissipation, delay and area of the 7-transistor SRAM memory cell at 90 nm technologies by using the Tanner tool. The article targets towards short circuit power dissipation as well as switching power dissipation. The circuit is characterized by using the 90 nm technology which is having a supply voltage of 1.0 volts and threshold voltage is 0.3 volts.

Dynamic logic circuits are preferred over CMOS static logic circuits due to the low area and high-speed advantage they offer in high-performance designs. In electronics circuits, the power dissipated by the clock plays a crucial role, and hence research approach in this paper is predominantly centered on the examination of the dynamic logic circuit's comparative performance. This presented work uses the tanner tool to present a novel phase detector (PD) and phase-frequency detector (PFD) using dynamic logic architecture in standard 250nm and 45nm technology. The presented approach optimizes the circuit's speed and power by customizing the conventional approach. The transistor count has been dropped, resulting in lower power consumption and a smaller layout. All the circuit performances like transistor delay, power dissipation, the figure of merit has been optimized. Optimized results are glitch-free and enhance the performance of the circuit. The power supply voltage Vdd is varied in the range of 0.6-1.4 volts and the W/L value for PMOS and NMOS is varied within 1 and 5 to analyze its power and delay performances. These results presented the best possible trade-off between the proposed design in comparison to other existing techniques to optimize area, power, and speed for VLSI circuits.

In the present scenario, the devices supporting neighbor discovery are going through the renovation phase, and crossing the classical barrier such as the trade-off between power dissipation and access time. The presence of opportunistic nodes in place of static nodes has presented multiple challenges for such devices. Therefore, the focus of neighbor discovery has mostly shifted toward such issues where power dissipation and latency of mobile nodes need to be simultaneously improved to achieve uninterrupted and quality communication. Since static random-access memory (SRAM) is an integral part of all such sensor nodes and directly impacts power dissipation and latency, therefore in this paper, we have introduced a novel SRAM cell for such nodes. The proposed eleven transistors (11T) SRAM cell is compared with six recently reported designs to check the improvement of SRAM key design parameters. The compared designs include Standard 6T (S6T), tunable 8T(TU8T), PPN-based 10T (PN10T), Schmitt trigger-based 10T (S10T), bit-line-dependent 11T (DP11T) bit-cell and stable low power 11T (SP11T). The improvement in write ability and read stability of proposed 11T cell is represented by [Formula: see text] and [Formula: see text] enhancement of write and read static margins, respectively, in comparison to S6T/TU8T/PN10T/S10T/DP11T/SP11T. Further, the leakage power dissipation is reduced by [Formula: see text] as compared to S6T/TU8T/S10T/PN10T/DP 11T/SP11T. Additionally, power dissipation and delay of proposed 11T cell during read operation is reduced by [Formula: see text] and [Formula: see text], respectively, as compared to S6T/TU8T/PN10T/S10T/DP11T/SP11T. It is worth mentioning here that the proposed 11T also shows narrower variability in power dissipation and current values during read operation comparing S6T. The proposed 11T design successfully mitigates the half-select issue and allows the SRAM array to attain the bit-interleaved architecture implementation.

High power dissipation has become key role in VLSI design circuits, when it comes to battery -operated applications it is important to save the battery life.Short -circuit power and switching power play key role in power dissipations, there are so many techniques to reduce power.By stacking arrangement, we can reduce power and we can utilize technique for various circuits.In this paper NAND and NOR gates realized, stacking technique consumes low power than standard reduction techniques.These circuits are simulated in Tanner EDA Tool with generic 250 nm transistors.

R-C snubber circuits are used to absorb the reverse recovery energy of a rectifier diode and limit the associated voltage spike across it as presented by MacMurray (1972). This circuit, while being simple and reliable is unsuitable for applications with power levels above 10 kW due to its high power dissipation. Existing alternatives efficiently recycle the diode reverse recovery energy into the load. However, these suffer from drawbacks such as excessive diode voltage stress or circuit complexity. This paper proposes a reduced rating diode snubber that limits the diode voltage stress over the entire load operating range while keeping the snubber power dissipation to a minimum. A simple circuit model is simulated to evaluate its operation over the entire power supply operating range. It is first experimentally verified with a proof-of-concept 7 kW prototype. Experimental results show a 60 % reduction in power dissipation in addition to a 30 % reduction in diode voltage overshoot when compared with the conventional R-C snubber under nominal operating conditions. Further experimentation with a 100 A, 150 V plasma cutting power supply shows that the output rectifier voltage stress is kept within reasonable limits over a wide load operating range verifying the robustness of the proposed circuit.