Adopting System Call Based Address Translation into User-Level Communication

A short time-to-market is very important for a chip, and verification takes the most (about 70%) of its design time. Network interface controller (NIC) is a key component for a supercomputer and other computing systems. To reduce verification time for such a market-demanding product plays a great role in relevant system design. In this paper, a functional verification accelerator NICFlex is presented for a register transfer level (RTL) NIC design. NICFlex accelerates verification process by both a software part and a hardware part. The software part runs as a simulation thread, and the hardware part is mapped into field programmable gate array (FPGA) logic together with a NIC wrapper. Compared to a conventional simulation verification method using ModelSim, NICFlex can accelerate the functional verification of an RTL NIC design for hundreds of times or more. With extension, NICFlex is promising for any functional verification acceleration of a generic RTL design.

A media access control address (MAC address) is a unique identifier assigned to network interfaces for communications on the physical network segment. MAC addresses are most often assigned by the manufacturer of a network interface controller (NIC) [1]. In traditional Ethernet network, there is a security vulnerability that allows attackers to easily generate forged frame because they can know MAC address of hosts in the subnet. In this study, we have designed new communication method using a virtual MAC address in order to complement a disadvantage of the traditional Ethernet communication. Hosts generate the frame hiding the MAC address of the header field and encrypting the data field to prevent attacks using forged frame in the subnet.

Recent advances in commodity network interface technology enable scientists and engineers to build clusters of workstations or PCs to execute parallel applications. However, raw-hardware network performance is rarely delivered to applications because of the overheads of communication software and operating systems. To reduce these overheads, a technique called user-level communication can be used to allow applications to access the network interface directly without intervention from the operating system. We examine two user-level communication systems, GM and BIP, on alpha based systems connected by a Myrinet network. In addition quantitative studies on how DMA initiation costs, flow control and reliable communication will effect the performance of communication software are presented.

This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kernel-based performance optimization.We believe that this approach is more likely to meet the needs of current and future high-bandwidth TCP/IP networking on end hosts than the current trend of putting more complexity in the NIC, while avoiding the need to modify applications and protocols. This paper presents two such NICs. The first, the simple integrated NIC (SINIC), is a minimally complex design that moves the responsibility for managing the network FIFOs from the NIC to the kernel. Despite this closer interaction between the kernel and the NIC, SINIC provides performance equivalent to a conventional DMA-based NIC without increasing CPU overhead. The second design, V-SINIC, adds virtual per-packet registers to SINIC, enabling parallel packet processing while maintaining a FIFO model. V-SINIC allows the kernel to decouple examining a packet's header from copying its payload to memory. We exploit this capability to implement a true zero-copy receive optimization in the Linux 2.6 kernel, providing bandwidth improvements of over 50% on unmodified sockets-based receive-intensive benchmarks.

Modern high speed local area networks offer great potential for communication intensive applications, but their performance is limited by the use of traditional communication protocols, such as TCP/IP. In most cases, these protocols require that all network access be through the operating system, which adds significant overhead to both the transmission path (typically a system call and data copy) and the receive path (typically an interrupt, a system call, and a data copy). To address this performance problem, several user level communication architectures have been developed that remove the operating system from the critical communication path. The article describes six important issues to consider in designing communication protocols for user level architectures. The issues discussed focus on the performance and semantics of a communication system. These issues include data transfer, address translation, protection, and control transfer mechanisms, as well as the issues of reliability and multicast. To provide a basis for analyzing these issues, the authors present a simple network interface protocol for Myricom's Myrinet network, which has a programmable network interface. Researchers can thus explore many protocol design options, and several groups have designed communication systems for Myrinet. The authors refer to 11 such systems, all of which differ significantly in how they resolve these design issues but all of which aim for high performance and provide a lean, low level, and more or less generic communication facility.

The classical paging problem, introduced by Sleator and Tarjan in 1985, formalizes the problem of caching pages in RAM in order to minimize IOs. Their online formulation ignores the cost of address translation: programs refer to data via virtual addresses, and these must be translated into physical locations in RAM. Although the cost of an individual address translation is much smaller than that of an IO, every memory access involves an address translation, whereas IOs can be infrequent. In practice, one can spend money to avoid paging by over-provisioning RAM; in contrast, address translation is effectively unavoidable. Thus address-translation costs can sometimes dominate paging costs, and systems must simultaneously optimize both. To mitigate the cost of address translation, all modern CPUs have translation lookaside buffers (TLBs), which are hardware caches of common address translations. What makes TLBs interesting is that a single TLB entry can potentially encode the address translation for many addresses. This is typically achieved via the use of huge pages, which translate runs of contiguous virtual addresses to runs of contiguous physical addresses. Huge pages reduce TLB misses at the cost of increasing the IOs needed to maintain contiguity in RAM. This tradeoff between TLB misses and IOs suggests that the classical paging problem does not tell the full story. This paper introduces the Address-Translation Problem, which formalizes the problem of maintaining a TLB, a page table, and RAM in order to minimize the total cost of both TLB misses and IOs. We present an algorithm that achieves the benefits of huge pages for TLB misses without the downsides of huge pages for IOs.

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use of Accelerated Processing Units (APUs), processors that incorporate both a central processing unit (CPU) and an integrated graphics processing unit (iGPU). However, the performance of both APU and CPU systems can be significantly hampered by address translation overhead, leading to a decline in overall performance, especially for cache-resident workloads. To address this issue, we propose the introduction of a new intermediate address space (IAS) in both APU and CPU systems. IAS serves as a bridge between virtual address (VA) spaces and physical address (PA) spaces, optimizing the address translation process. In the case of APU systems, our research indicates that the iGPU suffers from significant translation look-aside buffer (TLB) misses in certain workload situations. Using an IAS, we can divide the initial address translation into front- and back-end phases, effectively shifting the bottleneck in address translation from the cache side to the memory controller side, a technique that proves to be effective for cache-resident workloads. Our simulations demonstrate that implementing IAS in the CPU system can boost performance by up to 40% compared to conventional CPU systems. Furthermore, we evaluate the effectiveness of APU systems, comparing the performance of IAS-based systems with traditional systems, showing up to a 185% improvement in APU system performance with our proposed IAS implementation. Furthermore, our analysis indicates that over 90% of TLB misses can be filtered by the cache, and employing a larger cache within the system could potentially result in even greater improvements. The proposed IAS offers a promising and practical solution to enhance the performance of both APU and CPU systems, contributing to state-of-the-art research in the field of computer architecture.

Processor-embedded distributed smart disks for I/O-intensive workloads: architectures, performance models and evaluation

The cloud computing is one of the most popular issues in recent years. Many service providers have provided the cloud solution using virtualization such as Amazon EC2. We are facing the new threats in the virtual environment. Since the virtual network is different to the traditional environment, we have to face with new threats that do not exist in the traditional network environment. In this paper, we provide a solution Virtual Network Guard System (VNGS) to solve the problems in virtual network that we face in the virtual environment. We modify the network interface controller in the virtual environment to limit the guest operation system access rights. We also provide a centralize management server to deploy filtering processes and collect the alert information. Finally, we evaluate the performance of our system with normal network interface controllers, and the results shows that the performance is acceptable.KeywordsCloud SecurityPacket FilterVirtual Network Security System

The paper is dedicated to analysing possible tools for cyber threat prevention with the combination of hardware accelerators to support this activity. Perspectives on using Intrusion Detection Systems (IDS) and Intrusion Prevention Systems (IPS) are discussed. The signature method and anomaly detection method are analysed. An analysis of hardware accelerators based on Field Programmable Gate Array (FPGA) is conducted. The use of Smart Network Interface Controller (NIC) is discussed. The set of the most popular Original Equipment Manufacturer (OEM) of FPGA-based SmartNICs is considered. The possibility of the use of Open Cyber Threat Intelligence (OpenCTI) platform is discussed. A system structure for preventing implementations of known cyber threats using the FPGA and OpenCTI framework is studied. A sequence of steps for creating hardware-accelerated solutions to prevent implementations using information from OpenCTI-based databases is proposed.

A parallel rough set based dependency calculation method for efficient feature selection

In this work, we present a set of techniques that considerably improve the performance of executing concurrent MapReduce jobs. Our proposed solution relies on proper resource allocation for concurrent Hive jobs based on data dependency, inter-query optimization and modeling of Hadoop cluster load. To the best of our knowledge, this is the first work towards Hive/MapReduce job optimization which takes Hadoop cluster load into consideration. We perform an experimental study that demonstrates 233% reduction in execution time for concurrent vs sequential execution schema. We report up to 40% extra reduction in execution time for concurrent job execution after resource usage optimization. The results reported in this paper were obtained in a pilot project to assess the feasibility of migrating A/B testing from Teradata + SAS analytics infrastructure to Hadoop. This work was performed on eBay production Hadoop cluster.

Most of users are accustomed to utilize the virtual address in their parallel programs running at the exascale computer systems. Therefore the virtual and physical address translation mechanism is necessary and crucial to bridge the hardware interface and software application. We proposed a novel two-level concurrent address translation Cache (TLC) for high performance interconnect network–TH Express-2. The TLC is composed of L1 Cache (L1C) and main eDRAM-based Cache (MEC). A fast and small L1 Cache implemented by high-speed SRAM is adopted. The MEC employs the large capacity eDRAM (embedded Dynamic Random Access Memory) macros to meet the high hit ratio requirement. To avoid the stall incurring by refresh collision, a novel eDRAM stall-hidden refreshing algorithm is proposed. Many tests have been conducted on the real chip implementing TLC. The results show that the MEC has high hit ratio and L1C has considerable hit ratio while running the well-known benchmarks. Owing to the L1 Cache involved, the total runtime of TLC is reduced about 14%, only at the cost of 1.2% area occupied.

The demand for higher computing power and, thus, more on-chip computing resources; is ever increasing. The size of on-chip cache memory has also been consistently increasing to keep up with developments in implementation technology. However, some applications may not utilize full cache capacity and, on the contrary, require more computing resources. To efficiently utilize silicon real-estate on the chip, we exploit the possibility of using a part of cache memory for computational purposes to strike a balance in the usage of memory and computing resources for various applications. In an earlier part of our work, the idea of adaptive balanced computing (ABC) architecture was evolved, where a module of an L1 data cache is used as a coprocessor controlled by main processor. A part of an L1 data cache is designed as a reconfigurable functional cache (RFC) that can be configured to perform a selective core function in the media application whenever such computing capability is required. ABC architecture provides speedups ranging from 1.04x to 5.0x for various media applications. We show that a reduced number of cache accesses and lesser utilization of other on-chip resources, due to a significant reduction in execution time of application, will result in power savings. For this purpose, we first develops a model to compute the power consumed by the RFC while accelerating the computation of multimedia applications. The results show that up to a 60 percent reduction in power consumption is achieved for MPEG decoding and a reduction in the range of 10 to 20 percent for various other multimedia applications. Besides, beyond the discussions in earlier work on ABC architecture, we present a detailed circuit level implementation of the core functions in the RFC modules. Further, we go much further and study the impact of converting the conventional cache into RFC on both access time and energy consumption. The analysis is performed on a wide spectrum of cache organizations with size varying from 8KB to 256KB for varying set associativity.

Internet of Things IoT is a model of future internet and pervasive computing which have its own challenges derived from the internet in terms of scalability, undefined topology and so on. The proposed work aims to resolve the challenges posed by IoT in service discovery functionality. Considering the pervasive and context dependent nature of IoT the planned work bases its development strategy using an aspect oriented software development methodology. The novelty lies in achieving high degree configuration and customisability by selecting subset of middleware functionality depending on the need. The performance is compared with MUSIC pervasive computing middleware and Android built-in configuration. The result reveals 6.5% decrease on average boot up and reconfiguration time for smart phones and 11.6% percentage decrease in Android tablets. In the context of boot up and reconfiguration time the middleware brings out 5% decrease for smart phones and 3% for Android tablets when compared with MUSIC middleware. The middleware shows 6.3% and 4% reduction in execution time of applications on smart phones and tablets when assessed with MUSIC middleware.