An Active Analog Filter Architecture Ensuring Unity-Gain and Low Sensitivity

This paper presents a case study on back gate or body bias variation on the performance of a two stage Class AB Folded Cascode operational amplifier in 22nm FD-SOI (fully depleted silicon on insulator) technology. The back gate bias is varied on each of the op-amp (operational amplifier) building block and its impact on the overall op-amp performance is observed. Finally the performance of the op-amp with back gate bias and without back gate bias are compared. The primary output parameters measured are open loop gain, unity gain bandwidth, settling time (12 bit), output range, phase margin and power consumption. While most of the parameters remain nearly constant, or do not change much, there is a tuning range of 6dB for open loop gain, the input range of 325mV can be shifted by around 110mV and settling time can be varied by 15%.

The heartbeat has frequency from 0.1 Hz to 150 Hz. The electrical signal which is resulted from the heartbeat has amplitude of 100μV - 4 mV. In order that the amplitude can be sampled by the ADC, it must be amplified 100 times, thus amplitude amplifier about 60dB it is required. In this research, the researcher designs a System on Chip ECG based on Einthoven method which has 3 Leads, so amplitude can be amplified based on the different voltage of each Lead. Differential amplifier is an initial amplifier that will amplify the difference of two inputs of voltage. Differential amplifier is designed using 3 operational amplifiers (op-amp). Op-Amp A1 and Op-Amp A2 are used for detecting and sampling the difference of two input levels. The function of Op-Amp A3 is to amplify the difference results of the sampled input level. Op-Amp A1, Op-Amp A2 and Op-Amp A3 are designed with offset voltage of Vos ≈ 0V, Open Loop Gain ≈ 66.42 dB, Phase Margin ≈ 400 and Unity Gain Bandwidth ≈ 160.7MHz. Method of the research is design and simulation using 0.35 micro Mentor Graphics technology. Result of the research is a layout of PreAmp for System on Chip ECG with gain of 62.4 dB and 0.034 mm2 area.

Operational Transconductane Amplifier (OTA) is a fundamental building block of analog signal processing application. This paper demonstrates a wide-linear-range low voltage subthreshold-mode based fully differential OTA using bulk-driven technique. The proposed OTA is linearly tunable with the feature of low distortion and high output impedance. The open loop gain of OTA is enhanced through use of improved Wilson current mirror. The OTA provides an increase in its linearity to about ±1.9 volt. The open loop gain is enhanced to 65dB at unity gain bandwidth (UGB) of 609.46 KHz. The proposed OTA operates at 0.9 volts and power consumption of the OTA remains in range of few hundreds of nanowatts. The OTA analysis has been performed in a standard TSMC 0.18 micrometer technology on BSIM 3v3 model using ELDO Spice Simulator.

Nanostructured polyaniline thin films as urea-sensing membranes in field-effect devices

A study was made of two micropowered operational amplifiers to determine degradation of unity gain frequency response, open-loop gain, and slow rate in amplifier circuits and maximum frequency of oscillation in Colpitts and Wein bridge oscillators as programmed. Quiescent current was reduced below specified operating levels into the nanoampere region.

We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a 1.8 V supply, post-layout simulations demonstrate an open-loop voltage gain of 97.23 dB, a 2.91 MHz unity-gain bandwidth (with a 1 pF load), and an input-referred noise of 4.75 μVrms. The total power dissipation, including bias circuitry, is 5.43 μW, and the amplifier occupies a chip area of 0.0055 mm2. Integrated into a conventional neural recording amplifier configuration, the proposed amplifier achieves a simulated input-referred noise of 5.73 µVrms over a 1 Hz to 10 kHz bandwidth with a power consumption of 5.6 µW. This performance makes it suitable for amplifying both action potential and local field potential signals. The amplifier provides an output voltage swing of 0.976 Vpp with a total harmonic distortion of −62.68 dB at 1 kHz.

This work deals with the design and analysis of large unity gain bandwidth operational amplifiers for low voltage applications. Conventional and dynamic threshold MOSFET (DTMOS) based design approaches of Op-Amp in sub-threshold and near-threshold regime have been chosen to achieve larger unity gain bandwidth. Extensive simulations have been done using TSPICE for 90nm and 180 nm separately.42 dB DC gain and 704 KHz unity gain frequency can be achieved in sub threshold region using proposed DTMOS structure. For lower technology node, i.e., for lower gate length of MOSFET, significant improvement in unity gain frequency has been observed. Simulated results demonstrate that the proposed op-Amp is suitable for the low voltage application which requires higher bandwidth. Besides, analysis of Op-Amp in near threshold regime would be promising for the IoT applications.

A bulk driven differential pair-based on OTAs with flipped, voltage flowers. Operational transconductance amplifiers (OTAs) for audio frequency applications are used in the signal stage. This article presents a simple and high performance conventional circuit for LP or LV efficient gates as well as a bulk-driven differential pair OTA (DPOTA) for applications of audio frequency. A composite transistor of the (FVFDP) flipped voltage follower differential pair is used to implement the summing stage, so it is capable of building the complete input as well as output dynamic range of (-VSS to VDD), which benefits the (FFV) bulk-driven OTAs of the inpu stage. Along with the design of the proposed OTAs is suitable for the operation of the CMOS transistor used to enhance the DC gain of the (FFV). OTAs, which is reduced the input referred to as noise (IRN) from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{0}.\mathbf{449}\boldsymbol{\mu}\mathbf{v}/\mathbf{sqrt}$</tex> (Hz) to 44.49nv/sqrt(Hz) at 100KHz. The transistor-level simulations performed using a 90nm CMOS process conform to the theoretical results of a cadence virtuoso environment. Simulated from a (0.7v to −0.7v) supply. These proposed conventional topology of the OTAs using an (SD) or source degenerative, resistor of 1k succeeds an open loop gain of 76.787 dB, it is seen the unity gain frequency (UGF) of 1.89 kHz and a phase margin of 78.07 companion capacitors is employed, gain bandwidth 14.04 kHz performed consumes at only 130.6nw of power.

This work describes how to generate and design a novel current-mode biquad filter model using tunable multiple-output operational transconductance amplifiers and grounded capacitors (MO-OTA-Cs) for synthesizing both transmission poles and zeros. Transfer functions of low-pass, band-pass, high-pass, notch and all-pass are realized based on the filter model. The theory focuses mainly on establishing a relationship between the cascaded MO-OTA-Cs and the multiple-loop feedback matrix, which makes the structural generation and design formulas. All the filter architectures contain only grounded capacitors, which can absorb parasitic capacitances and require smaller chip areas than floating ones. The simulation results are also presented to confirm the theoretical analysis.

Using specially designed broadband periodic random excitation signals, the open loop gain, and the common mode and power supply rejection ratios of operational amplifiers are measured and modeled. The proposed modeling technique 1) takes into account the measurement uncertainty and the nonlinear distortions, 2) gives information about possible unmodeled dynamics, 3) detects, quantifies, and classifies the nonlinear distortions, and 4) provides opamp parameters (time constants, gain-bandwidth product, etc.) with confidence bounds. The approach is suitable for the experimental characterization of operational amplifiers (see Part II) as well as the fast evaluation of new operational amplifiers designs using network simulators (see [12]). Part II handles the calibration of the experimental setup and illustrates the theory on real measurements.

Using a two-port active RC network containing one ideal differential input and output operational amplifier, realization procedures are developed for simultaneous realization of any pair of the four short-circuit admittance parameters. The only stipulation on the parameters is that they must be real rational functions in the complex frequency variable. Experimental verification of one of the procedures is presented. The procedures are generalized to the N- port case in order to show that one amplifier and an RC network are sufficient for the simultaneous realization of any N admittance parameters provided one parameter is prescribed from each column (row) of the admittance matrix of the active N- port network, but proof appears in (10).

Raman competition from ultra-broadband modulation instability gain in the As2Se3 glass photonic crystal fiber filled with argon gas

Operational amplifiers are critical components in modern analog electronics, widely used across applications such as signal conditioning, instrumentation, voltage regulation, and analog-to-digital conversion. This paper presents the design, development, and evaluation of the aRD820, a low-power, rail-to-rail operational amplifier, as a cost-effective alternative to the industry-standard AD820. The aRD820 is optimized for operation on a single supply voltage ranging from 5 to 30 V or a dual supply of ± 2.5 V to ± 15 V. Key design objectives included achieving low voltage noise (&lt; 4 µV peak-to-peak from 0.1 to 10 Hz), ultra-low input bias current (&lt; 15 pA), and a low offset voltage (&lt; 500 µV), make it suitable for high-sensitivity applications. In adapting the AD820 design, RD Alfa Microelectronics addressed specific production constraints by modifying key circuit elements to meet the specifics of available production facilities. The modified input stage reduced noise by incorporating source followers, enhancing the allowable input signal range. Adjustments to the second and output stages improved the phase stability and characteristics. Extensive testing of the aRD820 in both wafer form and TO-5 packaged chips confirmed that the amplifier meets or exceeds planned specifications. Comparative results demonstrate that the aRD820 provides open-loop gain, offset voltage stability, and output saturation voltages comparable to those of the AD820. Noise measurements yielded values within the planned range, with an input noise density of approximately 13.5-18.1 nV·Hz-0.5, suitable for applications requiring precision signal processing. This paper provides a comprehensive overview of the design modifications and test results, establishing the aRD820 as a viable alternative to existing op-amps in similar applications.

Low-dropout (LDO) regulators have become integral parts of on-chip power management schemes. This paper presents a capacitor-less LDO regulator, which incorporates a Class AB input stage cross-coupled differential amplifier to improve slew-rate and a passive low-pass RC filter to improve the power supply rejection ratio (PSRR). The high DC gain of the class AB input operational transconductance amplifier (OTA) improves the PSRR of the LDO to about 45 dB @ 100 kHz. In addition, a PMOS pass transistor is cascaded with an NMOS device to improve the PSRR and the concept of miller capacitance is used to stabilize the LDO with small load capacitor of 10pF. From the initial simulation results, it has been observed that the proposed LDO can operate from a supply voltage of 3.3–3.5 V with a minimum dropout voltage of 0.5 V at a maximum 50-mA load and quiescent current of 50 μA.

Chapter 25 - Common Application Mistakes