An approximation algorithm for the balanced Max-3-Uncut problem using complex semidefinite programming rounding

The m‐way graph partitioning problem is of central importance in combinatorial optimization. It has many important applications in fields such as VLSI circuit design, task allocation in distributed computing systems, and network partitioning. In this paper, we propose an efficient genetic algorithm to solve this problem. The proposed method searches a large solution space and finds the best possible solution by adjusting the intensification and diversification automatically during the optimization process. The proposed method is tested on a large number of instances and compared with some existing algorithms. The experimental results show that the proposed algorithm is superior to its competitors in terms of computation time and solution quality. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

Due to high packaging density of components, power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. While most analysis focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. At higher frequency of operations, of the order of few GHz, the interconnect is to be analyzed with a distributed RLCG model. Because at very high frequency, the dielectric material deviates from it's ideal nature. This gives rise to the shunt conductance matrices. In this paper we have considered the high frequency effects and modeled the interconnect as distributed RLCG segments to compute the interconnect power dissipation. The results obtained from SPICE simulation justify the accuracy of our model.

This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. The designed voltage reference circuit achieves a reference voltage of 550 mV with 600 nW power dissipation. The reference voltage variation of 8.18% is observed due to temperature variation from −40°C to + 125°C. The MDEA-based optimal design of RO oscillates at 2.001 GHz frequency, has a phase noise of −87 dBc/Hz at 1 MHz offset frequency, and consumes 71 μW power. This work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifications are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.

Finding global optimum of a non-convex quadratic function is in general a very difficult task even when the feasible set is a polyhedron. We show that when the feasible set of a quadratic problem consists of orthogonal matrices from $${\mathbb{R}^{n\times k}}$$ , then we can transform it into a semidefinite program in matrices of order kn which has the same optimal value. This opens new possibilities to get good lower bounds for several problems from combinatorial optimization, like the Graph partitioning problem (GPP), the Quadratic assignment problem (QAP) etc. In particular we show how to improve significantly the well-known Donath-Hoffman eigenvalue lower bound for GPP by semidefinite programming. In the last part of the paper we show that the copositive strengthening of the semidefinite lower bounds for GPP and QAP yields the exact values.

Sea-of-gates architecture

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

Simulators play an important role in the design of VLSI circuits, but they require a large investment of time and effort. In this work we present a high-level, Markov model of a protocol, and we show how the best performing design can be selected without the need for simulation. Novel is the way we model the combinational logic and buffers as separate components. We compute the power consumed by each component, as well as the area complexity and data throughput. As a case study, we formally model the industrial protocol AMBA, and generate 84 designs that fulfil certain correctness requirements. We predict the performance and area complexity of every design, and we compare our predictions with the results from simulation. A fidelity and linear regression analysis is used to compute the correlation between the predictions and simulations. We also consider the competing goals of low-power and high-throughput, and how to select a design that offers an optimal compromise.

The development of an MOS transistor charge and capacitance model for the analysis and design of VLSI circuits is described. The total stored charge in each of the gate, bulk, and channel regions is obtained by integrating the distributed charge densities over the thin-oxide area. Charge conservation is guaranteed in this model by using the terminal charges as the state variables. The capacitance expressions have the nonreciprocal property. Partition of channel charge into the drain and source components is 40/60 in the saturation region. In the triode region, this partition changes asymptotically to 50/50 as the gate voltage increases. The carrier-velocity saturation effect is incorporated through both the modification of channel quasi-Fermi level and the determination of drain saturation voltage. Implementation of the model in the SPICE circuit simulator has been achieved. Modeled results compare well with experimental data for transistors with channel lengths as small as 0.75 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

With the ever-increasing complexity, circuit verification at the full-chip level is a major bottleneck in the design of VLSI circuits. This paper presents procedures that verify a given CMOS/BiCMOS VLSI circuit for its compliance to a set of pre-defined rules or design styles. Predefined rules range from simple connectivity and sizing rules to specific circuit topologies ensuring acceptable circuit speed, reliability, and signal integrity. Our compliance checks operate on transistor-level circuit netlists, which may contain back-annotated parasitics. The procedures and rules have been implemented in a checker called Elecdra. VLSI circuits with over 3 million devices have been successfully verified by Elecdra at the full-chip level.

Since the beginning of the Seventies, the Microelectronics industry has followed Moore's law, doubling processing power every 18 months. This performance Improvement has been achieved by increasing the speed and decreasing the size of devices and circuits. The challenges faced by circuit and system designers were to achieve three basic aspects, e.g. speed, size and cost simultaneously in a single VLSI chip. The matter of power dissipation was less visible in early VLSI design issues. Power dissipation issue was not a design criterion. Power dissipation had taken a back seat as a figure of merit. High Speed operation and designing with minimum area, especially in memories, were the main design constraints. The state-of-the art was driven towards low cost and smaller chip area. Design tools were all geared towards achieving these two goals. With the emergence of mobile computing and communication devices, design and implementation of low power VLSI systems (in addition to the earlier three parameters) have got a significant role to play in VLSI circuit design.

We study the problem of computing correlation between two piecewise-linear bivariate functions defined over a common domain, where the surfaces they define in three dimensions---polyhedral terrains---can be transformed vertically by a linear transformation of the third coordinate (scaling and translation). We present a randomized algorithm that minimizes the maximum vertical distance between the graphs of the two functions, over all linear transformations of one of the terrains, in $O(n^{4/3}\\operatorname{polylog}n)$ expected time, where $n$ is the total number of vertices in the graphs of the two functions. We also present approximation algorithms for minimizing the mean distance between the graphs of univariate and bivariate functions. For univariate functions we present a $(1+\\varepsilon)$-approximation algorithm that runs in $O(n (1 + \\log^2 (1/\\varepsilon)))$ expected time for any fixed $\\varepsilon &gt;0$. The $(1+\\varepsilon)$-approximation algorithm for bivariate functions runs in $O(n/\\varepsilon)$ time, for any fixed $\\varepsilon &gt;0$, provided the two functions are defined over the same triangulation of their domain.

We are given a set of clients with budget constraints and a set of indivisible items. Each client is willing to buy one or more bundles of (at most) k items each (bundles can be seen as hyperedges in a k-hypergraph). If client i gets a bundle e, she pays bi,e and yields a net profit wi,e. The Hypermatching Assignment Problem (HAP) is to assign a set of pairwise disjoint bundles to clients so as to maximize the total profit while respecting the budgets. This problem has various applications in production planning and budget-constrained auctions and generalizes well-studied problems in combinatorial optimization: for example the weighted (unweighted) k-hypergraph matching problem is the special case of HAP with one client having unbounded budget and general (unit) profits; the Generalized Assignment Problem (GAP) is the special case of HAP with k = 1.Let e > 0 denote an arbitrarily small constant. In this paper we obtain the following main results:• We give a randomized (k + 1 + e) approximation algorithm for HAP, which is based on rounding the 1-round Lasserre strengthening of a novel LP. This is one of a few approximation results based on Lasserre hierarchies and our approach might be of independent interest. We remark that for weighted k-hypergraph matching no LP nor SDP relaxation is known to have integrality gap better than k − 1 + 1/k for general k [Chan and Lau, SODA'10].• For the relevant special case that one wants to maximize the total revenue (i.e., bi,e = wi,e), we present a local search based (k + O (√k))/2 approximation algorithm for k = O(1). This almost matches the best known (k + 1 + e)/2 approximation ratio by Berman [SWAT'00] for the (less general) weighted k-hypergraph matching problem.• For the unweighted k-hypergraph matching problem, we present a (k + 1 + e)/3 approximation in quasipolynomial time. This improves over the (k + 2)/3 approximation by Halldorsson [SODA'95] (also in quasipolynomial time). In particular this suggests that a 4/3 + e approximation for 3-dimensional matching might exist, whereas the currently best known polynomial-time approximation ratio is 3/2.

peer reviewed

Automatic detection of salient image regions is a useful tool with applications in intelligent camera control, virtual cinematography, video summarization and editing, evaluation of viewer preferences, and many others. This paper presents an effective method for detecting potentially salient foreground regions. Salient regions are identified by eigenvalue analysis of a graph Laplacian that is defined over the color similarity of image superpixels, under the assumption that the majority of pixels on the image boundary show non-salient background. In contrast to previous methods based on graph-cuts or graph partitioning, our method provides continuously-valued saliency estimates with complementary properties to recently proposed color contrast-based approaches. Moreover, exploiting discriminative properties of the Fiedler vector, we devise an SVM-based classifier that allows us to determine whether an image contains any salient objects at all, a problem that has been largely neglected in previous works. We also describe how the per-frame saliency detection can be extended to improve its spatiotemporal coherence when computed on video sequences. Extensive evaluation on several datasets demonstrates and validates the state-of-the-art performance of the proposed method.