An Approximation Algorithm with Factor Two for a Repetitive Routing Problem of Grasp-and-Delivery Robots

Printed circuit board (PCB) assembly lines consist of a number of different machines for mounting electronic components onto PCBs. While high-speed placement machines are employed to assemble standard components, so-called fine-pitch placement machines are used to mount complex electronic components with high precision and by use of specific nozzles. In this paper, we investigate a typical mass production environment where a single type of PCB is assembled in a line comprising high-speed as well as high-precision placement machines. The PCB assembly line balancing problem consists of assigning component feeders, each holding a specific electronic component type, and the corresponding placement operations to machines in the line so as to minimize the assembly cycle time. To solve this problem, a two-stage solution procedure based on genetic algorithm (GA) is proposed. In the first stage, component feeders are assigned to the placement machines with the objective of balancing the workload within the assembly line. A number of candidate solutions are then transmitted to the second stage, where specific machine optimization algorithms are applied to determine the feeder-slot assignment in the component magazine of the machines and the placement sequence of the various components. As a result, fine-tuned placement operation times are achieved which reflect the individual operation mode and the actual component setup of the placement machines. Finally, from the candidate solutions the one which minimizes the actual PCB assembly time is selected.

A description is given of the test concept and experimental validation of measurement techniques which exploit built-in-test (BIT) to simplify RF susceptibility measurements of complex digital integrated circuits (ICs) and printed circuit (PC) boards. The use of the BIT capability of VLSI devices and PC boards: (1) simplifies the hardware and software interfaces to the device-under-test; and (2) reduces the external test equipment requirements. A specific example is given as to how these techniques and procedures were applied to a self-testing Am2903 4-bit microprocessor slice test circuit. Test data are presented which demonstrate the feasibility of using BIT techniques to obtain susceptibility thresholds with a significant reduction in test complexity and external test equipment requirements. The limitations associated with using BIT techniques for susceptibility characterizations of ICs and PC boards are also addressed. >

One of the most important factors to give an inspection automation decision is the precision of measurements taken by the inspection machine. This paper aims to provide help in the selection of an automatic optical inspection (AOI) machine for a printed circuit board (PCB) assembly line of an electronics manufacturer. Since the visual inspection of soldered surfaces on a PCB is a crucial step, AOI machines bring great speed and accuracy to the inspection process. The main goal is to find the best automatic inspection machine alternative among the three AOI machine offerings according to nine selection criteria by integrating coefficient of variation statistic with TOPSIS and VIKOR, which are well-known multicriteria decision analysis methods. For this purpose, three different brands of AOI machines have been tested for the same PCBs, with 10 different components. After calculation of TOPSIS and VIKOR rank scores, the coefficient of variation of rank scores for all components is obtained and the selection of the AOI machine is finalized.

A high-density packaging approach has been developed that uses hermetic ceramic packages made with thick-film techniques. The overall packaging density, at the printed circuit (PC) board level, is comparable to or better than that achieved with some multichip packaging approaches. Low-cost thick-film ceramic packages are produced with no hard tooling from multiple sources. Chips are packaged, burned in, and tested in these packages with standard processes and production lines. The ceramic packages are then cut down to a smaller size by laser scribing and are mounted on printed circuit boards. The packages are then interconnected to the board by automatic gold-to-gold wire bonding. The author describes practical aspects of this packaging approach with respect to the design and fabrication of the thick-film ceramic packages, chip packaging and test using these packages, PC board design and fabrication, and PC board assembly. The issues of procurement costs, design, fabrication cycle times, parts screening, packaging density, rework, electrical considerations, thermal performance, process maturity, and reliability are also discussed. >

This project concerns the use of an electromagnetic sensor for the detection of leaks/cracks in water pipes. As old metal pipes corrode they start to become brittle, resulting in the potential for cracks to appear in the pipes. In addition corrosion can build up resulting in a restricted flow of water in the pipe. Using an electromagnetic (EM) wave sensor to monitor the signal reflected from the pipes in real time, provides the necessary information to determine where a leak in the pipe has occurred. Analysis of the reflected signal can provide the operator with information about the condition and position of a leak within the pipe. This is the first time research has been carried using EM waves for leak detection in water pipelines. This project involves the design and construction of an EM sensor operating at frequencies in the range of 240MHz to 560MHz, and at a power of OdBm. The sensor is launched into the water pipeline through any existing hydrant and is moved along the pipeline to check for leaks. The simulation software High Frequency Structure Simulator (HFSS) was used to model the pipe section as a circular waveguide cavity, and also for antenna simulation. The monopole and loop antenna were designed to determine the best antenna for this project. The printed circuit board (PCB) design package Eagle was used to provide the surface mount layout for the sensor, and the PCB board was fabricated by using a computer numerical control (CNC) routing machine. Finally the graphical interface package LabVIEW was used to control the frequency sweep for the sensor and to capture the data from the sensor. Based on the findings of this project, the EM wave sensor could be used to determine a leak up to a 0.9 correlation limit using low cost RF electronic devices.

In this paper, we consider a repetitive routing problem which we find on a printed circuit board assembly line. There are m different printed circuit boards to be processed. As an automated manipulator embeds electronic parts in a printed circuit board from above, n identical pins from underneath protect it against overbending. A dedicated pin configuration is designed for each printed circuit board so that pins do not obstruct its own circuit. A single grasp-and-delivery robot transfers the pins one by one to arrange them from a configuration to another one. Given an initial configuration of pins and a permutable set of m required configurations, our repetitive routing problem asks to find a configuration sequence, i.e., a processing order of m printed circuit boards, and a transfer route of the grasp-and-delivery robot so that the route length over all m transitions is minimized. We first design a polynomial time approximation algorithm with factor four to a restricted version of the repetitive routing problem with a non-permutable set of configurations, i.e., with a fixed processing order of m printed circuit boards. Applying the procedure, we then show that the repetitive routing problem with a permutable set of configurations admits a polynomial time approximation algorithm with factor six.

System-in-Package (SiP) is where multiple dice, along with passive components, are mounted onto a common substrate. For the purposes of testing, the substrate can be viewed as simply a printed circuit board. If viewed as such, there are two IEEE standards that can be used very effectively to provide testing of SiPs, (1) 1149.1 A Test Access Port and Boundary Scan Architecture, and (2) 1149.4 A Standard Mixed Signal Test Bus.

The rapid development of information and communication technologies has driven the rapid growth of data traffic and the large requirement of high-speed optical transceiver modules. Usually, optical subassemblies through flexible printed circuit boards (PCBs) connect with the hard PCBs to compose as optical transceiver modules. Because of the impedance mismatch of connection between flexible PCB and hard PCB, the operation bandwidth of the module can be limited. In this paper, the design of connection between flexible PCB and hard PCB in optical subassembly modules will be investigated for increasing the operation speed of the module. First, the transmission bandwidth of flexible PCB is analyzed. High-frequency performances of three transmission line structures, micro-strip line, grounded coplanar waveguide, and top ground micro-strip line, are investigated in flexible PCB. High-frequency performances of flexible PCB with different bending types are also investigated. The flexible PCB has been verified to be suitable to use in 25 Gb/s applications. Next, the high-speed transmission performance is analyzed through the connection between flexible PCB and hard PCB, because the impedance mismatch usually occurs at the connection. The ground pads are added near the signal line of flexible PCB, and the ground pads are connected to the ground layer in PCB through ground vias. The anti-pad in hard PCB is added under the signal solder pad. The dip of S21 response can be eliminated by the optimized ground pad. The impedance mismatch can be reduced by the optimized anti-pad, the impedance increases from 40-Ω to 49-Ω at the connection between flexible PCB and hard PCB, and the transmission bandwidth can increase from 16.5 GHz to 23.5 GHz. TO-46 header is a common and low-cost packaging solution for DFB laser and photodiodes. The connection between flexible PCB and TO-46 header is also investigated. While the connection has a gap, the dip of frequency response will occur at lower frequency. While the connection is very close, the bandwidth can be larger than 25 GHz. The flexible PCB, hard PCB, and TO-46 header are combined together, and the 23 GHz transmission bandwidth can be obtained. The 25 Gb/s transmission eye diagram is also measured, and the eye height, rise time, fall time, and Q-factor are 268.14 mV, 13.78 ps, 13.56 ps, and 8.76, respectively. The combined flexible PCB, hard PCB, and TO-46 header are verified to be suitable to apply in 25 Gb/s optical subassembly modules, and will be able to be used in 100G Ethernet.

Production planning and control of the printed circuit board (PCB) assembly includes several decisions dealing with, for example, grouping of PCB jobs, allocation of PCB batches to machine lines, sequencing of batches and load balancing of lines. The production time of a PCB job for a given placement machine is a key factor in this context and it must be quickly and accurately estimated, possibly millions of times in a single planning task, to avoid erroneous decisions. The commonly used nominal tact time-based estimators are very rough and the machine simulators too slow. Therefore, the purpose of this study is to give better machine-specific estimators that avoid the construction the actual machine control program. Two new estimators are proposed for gantry machines, one based on the information given by the manufacturer about the operations of the placement head, and the other on the regularised least-squares regression method trained with a set of PCB placement jobs. In practical evaluation with 95 PCB jobs, the mean absolute percentage error of the first and second methods are 3.75% and 6.52%, respectively, while that of the tact time-based approach is more than 17%. This indicates a great potential of the proposed methods as production time estimators.

Recent technological innovations, namely the development of new solder pastes with increased tack life and the introduction of bypass conveyors, facilitate the use of mixed-model lines in printed circuit board (PCB) assembly. This paper presents a simulation study comparing PCB assembly lines operating in conventional batch and in mixed-model assembly mode. For the latter case, a novel group setup strategy is developed. In the first stage, component types and placement operations for each type of PCB are assigned to the machines in the assembly line with the objective of balancing the workload. In the second stage, PCB types with similar component requirements are clustered into setup families. In addition, the feeder-slot assignment for each setup family and the sequence of placement operations for each PCB type are determined. In the final stage, a cyclical mixed-model production schedule is established. The performance of the proposed solution approach is evaluated by means of a simulation study. Two alternative material flow systems are investigated: a serial conveyor which directly links one machine to the other and a flexible one that allows to bypass downstream machines in the line.

In recent years, the development of low cost consumer electronic products such as television, mobile, washing machine etc. make high demands on manufacturing of defect free Printed Circuit Board and Printed Circuit Board Assembly. Therefore, it is necessary to know the different types of defects and defect detection techniques of Printed Circuit Board in order to produce high quality zero defect printed circuit boards. This paper discusses various methods which have been used in detecting defects so as to understand the gaps which would be helpful for the researchers to do the future work related to defect detection.

A Heuristic Algorithm to Balance Workloads of High-speed SMT Machines in a PCB Assembly Line

A Just-In-Time simulation model of a PCB assembly line

This paper discusses the component assignment problem for Printed Circuit Board (PCB) assembly lines in a computer manufacturing company. A PCB assembly line in the company has several non-identical pick-and-place machines to insert Surface Mounted Devices (SMD). On the other side, a board may have several hundreds of SMD components. Due to the various configurations of the machines, different machines have different unit assembly time for the same kind of SMD components. The question is how to assign these SMD components to those machines in order to achieve the best performance. The problem is formulated as a linear integer programming model in this paper. Although the objective of the integer programming can be the minimum balanced delay in a line balancing problem, we found the objective of minimizing cycle time to be better.

This paper investigates a multi-stage hybrid flow shop scheduling problem in a real-world printed circuit board (PCB) assembly shop. Some distinct characteristics such as calendar constraints, sequence-dependent setup times, unrelated parallel machines and stage skipping are taken into account. Besides, lot-sizing is introduced to split an order of PCBs into a number of smaller sub-lots to improve the utilization of the assembly lines. This article develops an effective hierarchical approach to reduce the complexity of such a complicated PCB scheduling problem by decomposing it into two highly coupled sub-problems of job sequencing and batch scheduling with lot-sizing. A two-stage ant colony algorithm with lot-sizing is proposed to evolve best results for makespan criterion. Extensive computational experiments have been conducted to compare the performance with two other algorithms. The results demonstrate that the proposed two-stage ant colony algorithm with lot-sizing is competitive in terms of computational result, computational time and stability.