An Automated and Process-Portable Generator for Phase-Locked Loop

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

Introduction Frequency synthesizers are pervasively utilized in almost every electronic system for generation of the well-defined clock frequencies of interest. For instance, in the modern wireless transceiver, a phase-locked loop (PLL) is commonly used to generate RF frequencies to up-convert and down-convert the analog signal. On the baseband side, the mixed-signal circuit, such as switched-capacitor filters, as well as digital VLSI also require PLLs to synthesize various clock domains. Moreover, the trend of future electronic design will continue to integrate more functionality, support multiple standards, and multi-channels in a system-on-chip (SoC) platform, which will inevitably increase the number of frequency synthesizers for various analog and digital circuit blocks. As a result, minimizing the power and area consumption of a frequency synthesizer becomes increasingly critical, or it can become the dominant cost factor in the overall system. This system trend has been driving PLL design towards more reconfigurability, wider tuning range and lower cost. The digitally-assisted PLL design concept becomes a natural consequence of this trend, as the flexibility offered via digital means is always appealing. Conventionally, the frequency synthesizer is implemented using an analog approach, i.e., the charge-pump PLL, as shown in Figure 4.1(a). The basic operation of this type of PLL has been well documented in textbooks and the literature [1, 2]. In brief, it processes the phase information in the analog domain via a phase frequency detector and a charge-pump circuit, so that the phase difference turns into current pulses. This current signal is then converted into voltage form via the analog loop filter, which typically consists of capacitor and resistor array. Some degree of digitally-assisted concept was adopted for this type of PLL, mainly to digitally reconfigure the analog loop filter and voltage-controlled oscillator (VCO). For example, the PLL may be required to support different PLL loop bandwidths and/or a wide VCO tuning range. The digitally switched capacitor or resistor bank is a common choice to support this kind of operation. While this analog PLL topology has been widely adopted and proven in both the literature and commercial products, it presents a challenge to scale with technology. The analog loop filter is typically composed of bulky passive components whose values are determined by the desirable PLL loop bandwidth, and cannot be arbitrarily reduced.

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

We propose a methodology that employs boolean minimization and optimized test covering to identify redundant tests of a mixed-signal circuit from its pass-fail (binary) test data. This methodology is applied to two in-production circuits, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL). Application of the methodology to over 38, 000 failing HSS circuits demonstrate that only 0.016% of them are mispredicted when three of nine high- voltage HSS tests are eliminated. Similarly, analysis of 22, 000 failing PLL circuits results in an error of 0.032% when 11 out of the 36 PLL tests are eliminated. Assuming 90% yield, these misprediction levels for the HSS and the PLL designs are equivalent to 16 and 32 DPM, respectively. The cost savings from eliminating the redundant tests in the HSS and the PLL designs at 90% yield are however estimated to be 21.9% and 30.9%, respectively.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

The Synchronization between the different sources, is an important task in Smart Grids application. However, the grid source is not a pure sinusoidal in the real case, and the deformation of the input signal due to the presence of harmonic frequencies caused by non-linear loads connected to the grid. There undesired frequencies are considered as a disturbance for the voltage grid, and needed to be filtrated to be able to detect the fundamental nominal frequency of the grid by the synchronization system. When disturbances occur, Power Sources necessitates appropriate control techniques in order to stay connected and contribute appropriately to overall grid stability. Furthermore, the disconnection of these sources due to synchronization problems could result a loss of energy generation. The control process is mostly dependent on synchronization algorithms, which must identify grid voltage state quickly and precisely (e.g., phase, amplitude, and frequency). Typically, Phase Locked Loop (PLL) synchronization techniques are commonly utilized for grid voltage monitoring. PLL design and performance have a direct impact on the Grid Side Converter (GSC). This paper presents an enhanced architecture of PLL used to synchronize Three-Phase Electric Power Sources under harmonically distorted grid condition. Finally, comparing to the classical architecture. MATLAB digital simulation results shows that the proposed architecture offers a 40dBm undesirable harmonics compensation and an enhancement of the three-phase signal purity from 14% to 0.01% of THD.

In this paper, a phase-locked loop (PLL) design using programmable frequency divider (FD) is implemented for low-power and high-speed wireless communication. The programmable FD of the PLL is designed with the use of extended true-single-phase-clock (E-TSPC) and the 4-1 multiplexer is designed with gate diffusion input (GDI). Optimized designs are used to minimize the power consumption of the PLL. The SPICE results illustrate that the PLL with GDI circuit consumed less power and delay of the order of 13.5 µW, 2.862 ns, respectively.

An optimized method to design and implement digital three-phase phase-locked loop (PLL) based on FPGA is presented in this paper. The PLL fits in electric power system as well as other fields. At first, principle and basic structure of the PLL including phase discriminator, loop filter and voltage controlled oscillator (VCO) are introduced, then these modules are designed in VHDL language with blocking design method. In order to save logic resource of FPGA, an optimized method called chip area sharing is adopted. At the same time, a new method which combines CORDIC algorithm with look-up table algorithm is put forward in this paper to generate sine function. This new method can both increase calculating speed and guarantee accuracy of results. At last, the design is implemented on Altera’s FPGA chip EP1C12Q240C8. It is verified that the design can save logic resource of FPGA largely, and it is also proved that the PLL can track the variation of frequency and lock the basic phase well.

The second-order generalized integrator (SOGI) with band-pass filtering characteristics is widely used in the design of advanced single-phase phase-locked loops (PLLs). But this type of PLL has insufficient ability to restrain dc biases, which limits their applications under certain conditions. Recently, a PLL adopting two cascade SOGI structures is called the cascaded generalized integrator PLL (CGI-PLL), which has perfect dc offsets blocking capability. However, the two output signals of the quadrature signal generator (QSG) formed by frequency-fixed CGI have different amplitudes, which makes the second harmonic oscillations appear in the estimated parameters of the PLL while the frequency deviates from the nominal frequency. Similarly, the in-phase output signal of CGI-based QSG is not synchronized with the fundamental frequency component of the grid voltage under frequency drifts, which is the reason for the phase offset error in the PLL outputs in the steady state. Some compensation strategies are added to correct the error that exists in the frequency-fixed CGI-PLL when the frequency deviates from the nominal value.

As an important factor for long-term jitter in clock synthesis and distribution, reference spurs result from circuit mismatch and nonlinear effects that induce periodic perturbations in phase-locked loops (PLLs). In this paper, a PLL with built-in static phase offset (SPO) detector and charge pump current trimming for self-calibration circuits is proposed. By adjusting the charge pump current ratio determined by an SPO detector, minimum and maximum improvements of 12dB and 22.99dB in reference spur suppression can be achieved. The best improvement reduces the integrated jitter by 10% over a 10kHz to 10MHz bandwidth. The technique is demonstrated for a PLL output frequency from 400 MHz to 1 GHz. The ring oscillator based PLL is designed with 200 KHz bandwidth and 70 degree phase margin. Measurement results from chips across different corners are provided to verify the calibration technique.

An integer-N phase-locked loop (PLL) is designed and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a complementary crossed-couple LC-tank voltage-controlled oscillator (VCO) and a mixed design of current mode logic (CML) and true single phase clock (TSPC) logic in the frequency divider achieves a fiber lasers application in microwave signal generation and intelligent computing from a free running mode-locked Er-fiber laser. In the stretched-pulse regime, the Er-fiber laser is designed at close-to-zero dispersion to minimize the phase noise of extracted microwaves. In order to suppress the excess phase noise in the optical to electronic conversion process, we synchronize a low-noise PLL to the fiber laser using a fiber Sagnac-loop-based optical-microwave phase detector.

Synchronization unit such as single-phase grid voltage phase-locked loop (PLL) is essential to control scheme in single-phase converters. However, the design of PLL is not simple and increases the complexity of control system, and the performance of PLL could be impacted by the waveform quality of the main voltage. Therefore, in this paper, a novel single-phase power calculation method without PLL is proposed to improve the performance of single-phase three-level rectifier which is widely used in railway traction drive system. Moreover, a strategy to compensate phase angle and power calculation error is presented to improve the power calculation precision and enlarge operation range. Then the compensation strategy and the single-phase power calculation method are combined with a common direct power control (DPC) to form a no-PLL control system for single-phase three-level rectifiers. Finally, performance of the proposed scheme is verified through experimental tests and compared with two traditional PLL-based control schemes.

Three independent research groups have proposed three apparently different architectures for an improved phase-locked loop (PLL) structure through three entirely different approaches. It is shown that all three PLLs are structurally and mathematically the same. A linear analysis is performed and concludes that the available theory for the design of conventional PLLs can be leveraged into the design of the new class of PLLs.

A 1-GHz phase-locked loop (PLL) is implemented in 0.5-/spl mu/m CMOS to generate a 500-MHz clock with 50% duty. The voltage-controlled oscillator (VCO) combined with the differential charge pump is employed to have low clock skew and better immunity to the noises from supply, ground and substrate. The long-term peak-to-peak jitter of less than 70 psec and 165 psec are achieved for the quiet supply line and for the noisy one modulated by 400-mV/sub p-p/, 500-kHz square wave, respectively. The prototype 1-GHz PLL consumes 55 mW with 3.3-V supply. The PLL with the phase interpolation technique is also investigated and its performance is compared to the standard approach.

This chapter provides an integrated overview of the fundamentals of global navigation satellite system (GNSS) signal tracking and the latest developments in advanced signal tracking techniques to improve sensitivity, robustness, and accuracy of performance. It begins with the objectives of signal tracking, followed by a conceptual description of a closed‐loop tracking system. A brief conventional treatment of code delay lock loop (DLL) is then presented. Carrier tracking is the more challenging and more intensely researched subject. The chapter summarizes the conventional phase lock loop (PLL) design. Tracking of simulated GPS L1 signals will be used to illustrate the concepts presented in the traditional implementations of DLL and PLL techniques. Following the conventional PLL description, the chapter presents a state space‐based feedback control theory to demonstrate that some of the popular carrier tracking loop implementations are fundamentally equivalent. Finally, it summarizes the latest developments in inter‐frequency aiding.