An exact analysis of Class-E power amplifiers for RF communications

The design of a new high-efficiency switching power amplifier with an ultralow-power spread spectrum clock generator (SSCG) is first reported in this paper. An effective low-power frequency modulation method is first proposed to reduce the electromagnetic interference of the pulse width modulation class D power amplifier without degrading its power efficiency. Also, a simple <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> voltage feedback circuit is used to reduce the total harmonic distortion (THD). This amplifier proves to be a cost-effective solution for designing high fidelity and high efficiency audio power amplifiers for portable applications. Measurement results show that the power efficiency and THD can reach 90% and 0.05%, respectively. The power dissipation of the SSCG is only 112 ¿W. The harmonic peaks of the switching frequency are greatly reduced when the SSCG technique is applied to the amplifier design. The impact of the SSCG on the THD of the class D power amplifier is also first reported in this paper. This switching power amplifier is implemented using a Taiwan Semiconductor Manufacture Company (TSMC) 0.35- ¿m CMOS process.

Preface. About the Authors. Acknowledgments. 1 Power Amplifier Fundamentals. 1.1 Introduction. 1.2 Definition of Power Amplifier Parameters. 1.3 Distortion Parameters. 1.4 Power Match Condition. 1.5 Class of Operation. 1.6 Overview of Semiconductors for PAs. 1.7 Devices for PA. 1.8 Appendix: Demonstration of Useful Relationships. 1.9 References. 2 Power Amplifier Design. 2.1 Introduction. 2.2 Design Flow. 2.3 Simplified Approaches. 2.4 The Tuned Load Amplifier. 2.5 Sample Design of a Tuned Load PA. 2.6 References. 3 Nonlinear Analysis for Power Amplifiers. 3.1 Introduction. 3.2 Linear vs. Nonlinear Circuits. 3.3 Time Domain Integration. 3.4 Example. 3.5 Solution by Series Expansion. 3.6 The Volterra Series. 3.7 The Fourier Series. 3.8 The Harmonic Balance. 3.9 Envelope Analysis. 3.10 Spectral Balance. 3.11 Large Signal Stability Issue. 3.12 References. 4 Load Pull. 4.1 Introduction. 4.2 Passive Source/Load Pull Measurement Systems. 4.3 Active Source/Load Pull Measurement Systems. 4.4 Measurement Test-sets. 4.5 Advanced Load Pull Measurements. 4.6 Source/Load Pull Characterization. 4.7 Determination of Optimum Load Condition. 4.8 Appendix: Construction of Simplified Load Pull Contours through Linear Simulations. 4.9 References. 5 High Efficiency PA Design Theory. 5.1 Introduction. 5.2 Power Balance in a PA. 5.3 Ideal Approaches. 5.4 High Frequency Harmonic Tuning Approaches. 5.5 High Frequency Third Harmonic Tuned (Class F). 5.6 High Frequency Second Harmonic Tuned. 5.7 High Frequency Second and Third Harmonic Tuned. 5.8 Design by Harmonic Tuning. 5.9 Final Remarks. 5.10 References. 6 Switched Amplifiers. 6.1 Introduction. 6.2 The Ideal Class E Amplifier. 6.3 Class E Behavioural Analysis. 6.4 Low Frequency Class E Amplifier Design. 6.5 Class E Amplifier Design with 50# Duty-cycle. 6.6 Examples of High Frequency Class E Amplifiers. 6.7 Class E vs. Harmonic Tuned. 6.8 Class E Final Remarks. 6.9 Appendix: Demonstration of Useful Relationships. 6.10 References. 7 High Frequency Class F Power Amplifiers. 7.1 Introduction. 7.2 Class F Description Based on Voltage Wave-shaping. 7.3 High Frequency Class F Amplifiers. 7.4 Bias Level Selection. 7.5 Class F Output Matching Network Design. 7.6 Class F Design Examples. 7.7 References. 8 High Frequency Harmonic Tuned Power Amplifiers. 8.1 Introduction. 8.2 Theory of Harmonic Tuned PA Design. 8.3 Input Device Nonlinear Phenomena: Theoretical Analysis. 8.4 Input Device Nonlinear Phenomena: Experimental Results. 8.5 Output Device Nonlinear Phenomena. 8.6 Design of a Second HT Power Amplifier. 8.7 Design of a Second and Third HT Power Amplifier. 8.8 Example of 2nd HT GaN PA. 8.9 Final Remarks. 8.10 References. 9 High Linearity in Efficient Power Amplifiers. 9.1 Introduction. 9.2 Systems Classification. 9.3 Linearity Issue. 9.4 Bias Point Influence on IMD. 9.5 Harmonic Loading Effects on IMD. 9.6 Appendix: Volterra Analysis Example. 9.7 References. 10 Power Combining. 10.1 Introduction. 10.2 Device Scaling Properties. 10.3 Power Budget. 10.4 Power Combiner Classification. 10.5 The T-junction Power Divider. 10.6 Wilkinson Combiner. 10.7 The Quadrature (90 ) Hybrid. 10.8 The 180 Hybrid (Ring Coupler or Rat-race). 10.9 Bus-bar Combiner. 10.10 Other Planar Combiners. 10.11 Corporate Combiners. 10.12 Resonating Planar Combiners. 10.13 Graceful Degradation. 10.14 Matching Properties of Combined PAs. 10.15 Unbalance Issue in Hybrid Combiners. 10.16 Appendix: Basic Properties of Three-port Networks. 10.17 References. 11 The Doherty Power Amplifier. 11.1 Introduction. 11.2 Doherty's Idea. 11.3 The Classical Doherty Configuration. 11.4 The 'AB-C' Doherty Amplifier Analysis. 11.5 Power Splitter Sizing. 11.6 Evaluation of the Gain in a Doherty Amplifier. 11.7 Design Example. 11.8 Advanced Solutions. 11.9 References. Index.

In this paper we discuss the advantages offered by GaN HEMT technology in the design of narrow- and wide-band high efficiency power amplifiers. On one side, we focus on the possibility of applying second harmonic tuning techniques without degradation of power performances, thanks to the GaN devices' high breakdown voltage. On the other hand, we discuss the impact of the high power density and consequent size reduction in GaN devices for the design of wideband power amplifiers. Three design examples are shown, to enforce the given considerations.

For the next generation applications in mobile communication, radar and satellite communication we need the devices that can operate at high frequencies and high power with minimum power consumption. There is a growing importance in the recent years for the development of GaN transistors.This paper presents design of the power efficient GaN based high power amplifier operating in the bandwidth of 5GHz – 7GHz based on a 12 Watt Discrete Power GaN on SiC HEMT from TriQuint. In this manuscript the design of RF power amplifier, its stability, input and output matching impedance and performance for 5-7GHz is presented. Design and simulations of the power amplifier are carried out using Advanced Design System (ADS). Simulation results of device stability, gain and Power Added Efficiency (PAE) shows good accordance with the specifications and parameters of the device.In the design process, for better correlation in measurement and simulation results precision of passive element models are specially considered. In 1 dB compression point for the designed high power amplifier, the experiment and the simulation results show a Power Efficiency of 68%.

<?Pub Dtl=""?> Design equations and performance limits of Class-E power amplifiers at mm-waves, including the limitations imposed by active and passive devices in a given technology, are presented in this paper. A beyond nominal breakdown voltage Class-E design methodology for SiGe HBT power amplifiers is proposed to generate high output power while maintaining high Class-E efficiency. A mm-wave SiGe stacked Class-E architecture is also introduced to increase the overall voltage swing, with each series stacked device operating in the beyond nominal breakdown mode. The mm-wave beyond <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$BV_{\rm CEO}$</tex></formula> operation of SiGe HBTs has been demonstrated experimentally in an integrated 45 GHz Class-E power amplifier fabricated in a 0.13 µm SiGe BiCMOS process with 20 dBm measured output power at 31.5% peak power-added efficiency (PAE). The series stacking of mm-wave Class-E power amplifier concept is also verified by fabricating double-stacked and triple-stacked SiGe HBT power amplifiers in 0.13 µm SiGe BiCMOS process which demonstrate a measured output power of 23.4 dBm at 41 GHz with peak PAE of 34.9%. High power, highly efficient, switching power amplifier unit cells presented in this paper can facilitate realization of efficient Watt-level mm-wave digital polar transmitters.

Developments within modern nonlinear measurement systems offer an increasing degree of flexibility to the microwave power amplifier (PA) designer. The PA designer has historically been a driving factor in setting the development directions of new measurement systems, fueling the paradigm, that PA innovations largely push new measurement requirements. It would appear that measurement system manufacturers are now the ones pushing the technology envelope. This paper discusses current trends within modern nonlinear measurement systems to determine who is leading whom and whether the aforementioned paradigm is shifting.

In this paper, an innovative approach to achieve broadband linear power amplifier (PA) with a continuous broadband is presented. The proposed method mainly depends on the theory of control of intermodulation products and harmonics. This method results in a continuous sweet spots over a wide bandwidth. Based on the continuous sweet spots, a suboptimal solution is derived for improving the efficiency and linearity of broadband PAs. To verify the effectiveness of this method, one broadband PA operating over 4.5–5.5[Formula: see text]GHz is developed and measured, it indicates that the peak output power of the PA is 35–57[Formula: see text]dBm for a small signal input with a gain of 12[Formula: see text]dB, and the peak drain efficiency (DE) of the PA is larger than 57% over the whole working band. However, when the PA is stimulated by a 5[Formula: see text]MHz two-tone signal input, we observe that the DE keeps above 38% under the condition of the measured third-order intermodulation distortion (IMD3) is not larger than [Formula: see text][Formula: see text]dBc.

A +15.1 dBm power amplifier (PA) operating at 70 GHz designed in a high speed digital InP HBT process is presented. The extraction of device models for the HBT's used in the PA design is discussed along with an electromagnetic simulation accounting for layout parasitics in the power cells. The design employs single-stage cascode amplifier topology in a finite ground CPW transmission line environment. The amplifier demonstrates the possibilities of utilising high speed digital InP HBT processes in the design of high frequency power amplifiers.

This thesis researches the design of transceiver front-end RF amplifiers for Bluetooth applications in GPDK 45 nm CMOS technology. The target of the design was to minimize the transceiver's power consumption while achieving the best device operating performances. The design of a band-pass low noise amplifier (LNA) used for the receiver and the design of a power amplifier (PA) used for the transmitter were presented. Both amplifiers were designed in 45 nm CMOS technology with a DC supply voltage under 1.2 V to meet Bluetooth specifications at 2.45 GHz operating frequency. The LNA was designed to achieve a minimum small signal gain of at least 15 dB10 with a NF less than 2 dB10 and a reasonable input range for linearity at 1 mW operating power consumption. The PA was designed based on class E switching power amplifier configuration to achieve a minimum of 40% drain efficiency for 100 mW (Bluetooth Class 1) output power. Research on low power high performance Bluetooth device front-end RF amplifiers was conducted through studies of wireless communication modulation schemes, impedance matching networks, and trade-offs between performance parameters. In summation, this thesis searched for, explored, and analyzed possible methodologies that could be used to design RF CMOS amplifiers of Bluetooth applications.

Radio frequency (RF) power supplies are important equipment in the semiconductor manufacturing process, and class E power amplifiers are widely used in RF power supplies due to their low switching losses. However, under the influence of parasitic parameters of class E power amplifier, soft switching is difficult to achieve. In RF high power applications, RF drivers are also difficult to design. In this paper, a soft-switching optimization method and a switch input impedance measurement method are proposed. The cascade structure of class E power amplifier is realized, and the sinusoidal output of the previous class E power amplifier is used to drive the second-stage class E power amplifier. In order to verify the validity of the theory, a class E power amplifier experimental prototype is built, with an output power of 2kW and an efficiency of 80.19%.

A series of novel continuous inverse modes based on current element is proposed. The series of novel continuous inverse mode is extended by increasing the coefficient in the current equation of traditional inverse class F power amplifier (PA). The theoretical analysis shows that new current equation can provide a wide matching space for the design of broadband high efficiency PAs. To prove this theory, a wideband high efficiency PA is designed and fabricated. The experimental test results show that the drain efficiency is 65-78% in the 1.8-3G frequency range. The designed PA can obtain output power from 12.9 to 21 W and gain is from 10 to 13.3 dB in the interesting frequency range.

WLAN is a widely used standard telecommunication protocol. Currently IEEE802.11ac standard has some limitations along with the increasing need for fast communication and able to serve many devices. The development of the IEEE 802.11ax standard is expected to overcome these limitations. Some challenges on the design of power amplifiers also appear as the development of 802.11ax standard. Power amplifiers on the access point are expected to provide a minimum output of 30dBm. This paper explains the design and modeling of power amplifiers on access point using load pull method. Based on the design and test result using CGH27030 transistor with simulation approach harmonic balance obtained that the output power of half wave obtained optimum value 33,023 dBm at input value 19 dBm and EVM equal to 4,8%.

In most of the applications, maximum power handling capability of gallium nitride (GaN)-based solid-state power amplifiers (SSPAs) is limited due to limitation of overall thermal management system. To utilize full power handling capability of GaN high power amplifiers, thermal management is a great concern to achieve best performance and more importantly to ensure required device reliability. This chapter presents thermal design aspects of GaN high power amplifiers at device and circuit design levels. Different thermal management schemes of high power amplifiers are discussed for efficient heat dissipation from GaN devices with high power densities.

This study presents an automated high-accuracy optimization approach for designing high-performance radio frequency high power amplifiers (HPAs). The amplifier is designed by applying a top-down pruning optimization approach that automatically converts the given HPA with lumped elements (LEs) to the HPA with distributed elements (DEs). Firstly, the lumped element HPA is designed based on a bottom-up optimization presented in Kouhalvandi et al. (2019 11th international conference on electrical and electronics engineering (ELECO), pp 510–513, 2019, 10.23919/ELECO47770.2019.8990407), then the LE amplifier is decomposed into basic unit cells that consist of one capacitor (C) and one inductor (L). For each LC unit, a suitable transmission line cell network is selected from predefined models by considering the maximum a posterior (MAP) metric. The component values of the resulting HPA design with DEs are optimized using Bayesian Optimization to achieve the desired design specifications. The overall proposed automated optimization accelerates the design process and outperforms the amplifier’s specifications that is constructed with DEs, automatically. The optimization starts with LE amplifier designs for keeping high linear gain performance and is converted to the HPA with transmission lines for having ready to fabricate circuit design. The proposed approach is validated by designing three HPAs with GaN HEMT from 1.8 to 2.2 GHz operational band frequency with drain efficiency more than 50% and with minimum linear power gain of 14.5 dB in all band frequency.

An L-band high power and high efficiency solid-state power amplifier (SSPA) design is presented. This compact, lightweight GaN HEMT SSPA is designed for nano-satellite GPS applications. This paper focuses on class F to achieve high efficiency by using waveform shaping methods. The optimal magnitude and phase of the fundamental, second and third harmonics (fo, 2fo and 3fo) are optimized by harmonic load-pull to produce a half-rectified sine wave for the drain current and a square wave for the drain voltage. To realize the design, a low impedance transformer with two harmonic traps are implemented by using second and third harmonic open circuit stubs. In CW, the SSPA can achieve 49W of saturated output power with gain of 17.2dB and PAE of 46.2% at 1.575GHz.