Performance Limits, Design and Implementation of mm-Wave SiGe HBT Class-E and Stacked Class-E Power Amplifiers

Introduction SiGe BiCMOS technology is an excellent choice for RF (radio frequency) and mm-wave applications as it combines the best features of CMOS logic, high-performance SiGe heterojunction bipolar transistors (SiGe HBTs), and RF passives like transmission lines, capacitors, inductors, Schottky barrier diodes (SBDs), p-i-n diodes, and resistors. RF models for all of these devices and process design kits are readily available for the design and simulation of RF circuits. In addition, BiCMOS technologies generally support multiple HBTs having different breakdown voltage, noise, and performance specifications for varied applications. The selection of any technology for mm-wave applications like power amplifiers (PAs) or transmitters is dependent not only on the performance of the technology but more so on the economics and total cost of the project integration. Compound semiconductor HBTs like InP and GaAs have better cut-off frequencies and breakdown voltage but lose to silicon technologies in terms of cost and integration. RFCMOS technologies may have similar performance specifications to the SiGe HBTs but BiCMOS is still preferred over RFCMOS for several reasons. At the same lithography node, SiGe HBT has superior performance and breakdown voltage to the CMOS devices. For equal performance CMOS requires much more aggressive lithography (> n + 2 gen) and as such is significantly more expensive than SiGe BiCMOS. SiGe HBTs have a higher breakdown voltage and power handling capability, higher operating voltage, higher self-gain, better voltage swing, better impedance matching, and better linearity than CMOS. This chapter will explore these and other aspects of the SiGe BiCMOS technology that make it ideal for silicon mm-wave applications like power amplifiers and transmitters. The chapter begins with a basic graded-base SiGe HBT device physics description followed by a discussion about the processing technology used to fabricate the device emphasizing aspects that impact high-performance mm-wave SiGe HBTs. A detailed comparison of performance trends across various technologies and industries is presented next. For mm-wave circuits there is an additional set of metrics such as breakdown voltage, noise figure, linearity, and thermal effects which are key to mm-wave applications. Several sections are devoted to discussion of breakdown voltage, thermal effects, and noise figure. In addition to the SiGe HBT transistors, silicon RF passives are also important and there is a discussion on Schottky diodes, PIN diodes, and other passives readily available in BiCMOS technologies.

This paper presents design and linearization techniques for a highly efficient but nonlinear class-E power amplifier (PA) applied to linear RF transmitters. A predistorted envelope modulation scheme is proposed to linearize the class-E PA. To accomplish this scheme, the class-E PA is designed with consideration of finite DC-feed inductance for wide supply-voltage modulation bandwidth. In addition, a digital envelope predistorter (DEP) is designed to provide the predistored envelope modulation for both RF-input and supply-voltage signals fed to the class-E PA. A cdma2000 1x transmitter incorporating such a Class-E PA and a DEP has been implemented to serve as an evidence for the simultaneous achievement of high efficiency and high linearity.

As the rapid development of 5G system and wireless communication technology, communication systems emphasize more on high-speed and stable information transmission and energy consumption, which directly promotes the update iteration of RF hardware design. As an energy-consuming device and the last stage device of the transmitter, the power amplifier determines the overall performance of the transmitter system. Theoretically, the class E power amplifier can reach 100% efficiency, the energy utilization rate is high, and it has the advantages of simple structure. Therefore, in the environment of highly integrated design and rapid development of mobile devices, Class E power amplifiers with high efficiency have gradually attracted people's attention. Based on 65nm CMOS process, a Class E power amplifier operating in 10GHz is designed. The Class E power amplifier includes a new adaptive self-biased circuit, which raises the average gate voltage of the common-gate transistor through the fast-charging branch. It reduces the on-resistance and the power loss during the charging process, therefore having great efficiency. This structure also maintains a certain voltage swing while increasing the gate voltage of the common-gate transistor. So, it controls the gate-drain voltage and gate-source voltage difference within a safe range during the entire signal cycle, avoiding the risk of breakdown of the gate oxide layer. As verified by Cadence Spectre simulation, under the 1.8V supply voltage, the output power of the Class-E power amplifier is 17.8 dBm, the gain is 12.6 dB, the second-order harmonic suppression is -33.7 dBc, and the power added efficiency is 41.2%,

This paper presents a CMOS inverter-like Class-D/E switching power amplifier (PA). The proposed amplifier operates in-between Class-E and Class-DE PAs. For proper operation of a Class-E PA, an RF choke (RFC) with large inductance value and high self-resonant frequency is necessary. A Class-DE PA does not require an RFC but requires a dead-time between OFF-ON transitions of the two switches. The proposed PA uses two complementary switches and requires neither an RFC nor a dead-time for its operation. For the same supply voltage and the load resistance, the voltage stress on each switching device in the proposed PA is less than the voltage stress in a Class-E PA. Design and simulation results of a prototype PA at 2.45 GHz with +20 dBm output power are presented.

This paper presents a new Class-E power amplifier (PA) with a π-matching output network. The PA is targeted at low output power wireless applications. Analytical formulae are derived to aid the PA design, characterization and optimization. A fully integrated 2.4-GHz PA for short distance communications has been implemented in 0.13 μm CMOS technology to verify the proposed design method. The measured output power levels vary from - 3.2 to 5.7 dBm while achieving maximum overall efficiency of 55%.

본 논문에서는 접지 결함 구조(Defected Ground Structure: DGS)를 이용하여 기지국용 고효율 E급 전력 증폭기의 성능을 유지하면서 크기를 소형화 할 수 있는 방안을 제안하였다. E급 전력 증폭기에서 요구되는 고조파 임피던스는 아령형 DGS와 나선형 DGS를 사용함으로써 만족시켜 주었다. 제안하는 유사 E급 전력 증폭기의 DGS 부하 회로는 가장 큰 고조파 성분인 2차 고조파 대역에서 개방, 나머지 고차 고조파 임피던스는 단락에 가까운 고조파 임피던스를 갖는다. 제안하는 구조를 통하여 제작된 전력 증폭기는 출력 전력이 43.1 dBm, 포화전력 이득이 12.7 dB일 때 70.2 %의 전력 부가 효율(Power Added Efficiency: PAE)을 가지며, 이는 비교 대상인 E급 증폭기와 거의 유사한 값이다. 회로 크기의 관점에서 보면 각각의 고조파 성분 정합을 위해 여러 개의 스터브가 장착되어 있는 비교 대상인 E급 증폭기에 비해 전체 크기를 50 %로 소형화시킬 수 있었다. In this work, a reduced size 20W quasi class-E Power Amplifier(PA) with defected ground structure load-network is presented for WCDMA base station application. Harmonic impedances required for the class E operation are satisfied by applying the dumbbell and the asymmetric spiral DGS. Open impedance for 2nd harmonic frequency which has the highest power and nearly short impedances for other higher order harmonics are provided by the proposed DGS load-network. The maximum Power Added Efficiency(PAE) of 70.2 % at the output power of 43.1 dBm with the saturated power gain of 12.7 dB is achieved by the proposed quasi class-E PA, which is comparable to the performance of the reference class-E PA. Total size of the proposed class-E PA is only <TEX>$50{\times}50\;mm^2$</TEX> and much smaller than the conventional class-E PA that is loaded with a number of open stubs.

This paper presents a new class of power amplifier (PA) - Class-iF- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> - resolving the highly nonlinear double inflection characteristics in the conventional Class-F- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> PA. It is illustrated that, by properly terminating the second harmonic source impedance Z <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2S</inf> from conventional short-circuit to open-circuit, the double inflection nonlinear gain profile can be mitigated in the proposed Class-iF- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> PA, wherein the same saturation output power is achieved with less gain compression without drain efficiency trade-off. The idea was validated with source/load-pull and a broadband prototype operating from 2.0 to 2.6 GHz was designed using a commercial 10-W Gallium Nitride (GaN) transistor. Under continuous wave (CW) signal test, the proposed Class-iF- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> PA can achieve 40.1-40.8-dBm output power, 71.2%-77.3% drain efficiency (DE) and 67.4%-74.1 % power added efficiency (PAE) at 3-dB gain compression level over 2.0-2.6 GHz.

The paper presents a design of a broadband high-efficiency class-E power amplifier (PA) for the advanced efficiency enhancement architectures applications. The design approach is based on presenting very high output reflection coefficient for a class E amplifier over broadband frequencies. An infinite reflection coefficient at load over the broadband frequency range enhances the application of class-E PAs as peaking amplifier in advanced efficiency enhancement architectures like Doherty, delta sigma etc. The proposed approach is validated using a Cree 6 W GaN prototype for a frequency band between 1.8–2.7 GHz. The prototype outputs more than 38 dBm output power with the drain efficiency higher than 55% over 40% of the fraction bandwidth. The drain voltage sweep of the fabricated PA shows that it can be also be employed in load modulated dual branch amplifiers and envelop tracking transmitter structures.

This paper presents a high efficiency class-E power amplifier (PA) suitable for wireless transmitters operating at 2 GHz. Compact impedance transformation network is designed, using micro-strip transmission lines, so that it simultaneously achieves fundamental load transformation and harmonic impedance control using only two open-circuit stubs (2fo, 3fo). The dimensions of the network’s elements were determined in order to concurrently attain a high harmonic suppression, minimum loss and high power added efficiency. The measurement results of the PA prototype, which is designed using a 10 W Gallium Nitride (GaN) HEMT transistor, showed state-of-the-art drain and power added efficiency (PAE). The achieved PAE, power gain and output power, when the drain is biased at 50V, were equal to 74%, 12.6 dB and 11.4W respectively. In addition, a second and third harmonic suppression in excess of −40 dBc and −75 dBc, respectively, is achieved without extra circuit tuning or additional filtering.

This paper presents a new approach to simplify the design of class-E power amplifier (PA) using hybrid artificial neural-optimization network modeling. The class-E PA is designed for wireless power transfer (WPT) applications to be used in biomedical or internet of things (IoT) devices. Artificial neural network (ANN) models are combined with optimization algorithms to support the design of the class-E PA. In several amplifier circuits, the closed form equations cannot be extracted. Hence, the complicated numerical calculations are needed to find the circuit elements values and then to design the amplifier. Therefore, for the first time, ANN modeling is proposed in this paper to predict the values of the circuit elements without using the complex equations. In comparison with the other similar models, high accuracy has been obtained for the proposed model with mean absolute errors (MAEs) of 0.0110 and 0.0099, for train and test results. Moreover, root mean square errors (RMSEs) of 0.0163 and 0.0124 have been achieved for train and test results for the proposed model. Moreover, the best and the worst-case related errors of 0.001 and 0.168 have been obtained, respectively, for the both design examples at different frequencies, which shows high accuracy of the proposed ANN design method. Finally, a design of class-E PA is presented using the circuit elements values that, first, extracted by the analyses, and second, predicted by ANN. The calculated drain efficiencies for the designed class-E amplifiers have been obtained equal to 95.5% and 91.2% by using analyses data and predicted data by proposed ANN, respectively. The comparison between the real and predicted values shows a good agreement.

This paper presents the design insights for the implementation of a monolithic radio frequency (RF) Class-E power amplifier for WLAN applications. The proposed high efficiency monolithic CMOS class-E power amplifier showcases the effective RF performance enhancement which is composed of two-stage structure and adopts a differential cascode topology with self-biased technique. The differential stage using differential cascode structure with current mirror can improve power gain and enhance the driving ability of switch stage. The switch stage utilizing self-biased technique and inserting a series LC networks on drain node of switch transistor considerable improve efficiency. This presented monolithic PA is simulated by Advanced Design System (ADS), designed and fabricated in the 0.18-μ RF CMOS process. The entire monolithic class-E PA system delivers maximum output power of 24.3dBm and the power added efficiency is 67.4% with 1.2 V supply. By optimizing element parameters, input and output have good matching features.

The effect of bias condition on total ionizing dose (TID) of Silicon–Germanium heterojunction bipolar transistors (SiGe HBTs) is investigated. The SiGe HBTs are set at forward, saturated, cutoff, and all-grounded biases during $^{60}{\hbox{Co}}\gamma $ irradiation. After each irradiation stops, the forward Gummel characteristic and inverse Gummel characteristic are measured, and a 3-D simulation of TID for SiGe HBT is performed. The mechanism of TID in different bias conditions is obtained by analyzing normalized excess base current. The results show that the TID damages are different at various irradiation biases of the SiGe HBT, and the worst bias between forward and inverse Gummel characteristics exhibits inconsistently. The reason could be attributed to different defects produced and accumulated in oxide layers by irradiation at various bias conditions. To be specific, the oxide trap charges ( ${{\hbox{N}}_{\rm ot}}$ ) in emitter/base (E/B) Spacer is important to the forward Gummel characteristic, yet the ${{\hbox{N}}_{\rm ot}}$ in LOCOS determines the inverse Gummel characteristic. However, after long time irradiation, the interface states ( ${{\hbox{N}}_{\rm it}}$ ) both in E/B Spacer and LOCOS dominate the damage to the SiGe HBT despite in forward Gummel mode or inverse Gummel mode.

Chapter 8 - Broadband Class-E

This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of <TEX>$0.4-{\mu}m$</TEX> and <TEX>$0.25-{\mu}m$</TEX> in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a <TEX>$0.25-{\mu}m$</TEX> transistor. The possibility of using a <TEX>$0.4-{\mu}m$</TEX> transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of <TEX>$0.4-{\mu}m$</TEX> transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the <TEX>$0.25-{\mu}m$</TEX> transistor.

In this study, an mm-wave band complementary metal–oxide–semiconductor (CMOS) power amplifier (PA) with a two-stage differential structure was designed. An analysis of the designed PA is presented and a new structure is proposed to eliminate the possibility of oscillation in the PA, which has high gain and high output power. The designed driver stage consists of a pair of cascode amplifiers and can be advantageously applied in beamforming systems as the PA phase is converted to 0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> /180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> with the on/off of a common-gate (CG) bias voltage. The power stage was designed with a three-stacked structure to obtain a high output power. The stability was improved using RC and capacitive feedbacks in the power stage. We implemented the PA using the 65-nm RF CMOS process. The designed PA used supply voltages of 2.0 and 3.3 V for the driver and power stages, respectively, and its saturated output power was measured as 24.7 dBm at 22.0 GHz. In this case, P <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{1\,dB}}$</tex-math> </inline-formula> was 20.6 dBm and the peak power added efficiency (PAE) was 26.0%.