An Improved Charge Pump with High Efficiency for Low Voltage Operations

For energy harvesting systems, a novel charge pump with cross-connected structure is proposed in this paper. Owing to the cross-connected structure, the proposed charge pump can offer the output voltage to the output load at every phase. Furthermore, the proposed charge pump can reduce the number of circuit stages from the conventional charge pump. For above-mentioned reasons, the proposed charge pump can realize not only smaller internal resistance but also smaller output capacitance than the conventional charge pump. The theoretical analysis and simulation program with integrated circuit emphasis (SPICE) simulation demonstrate that the proposed charge pump outperforms the conventional charge pump in the point of power efficiency and circuit speed.

In this paper, an improved four-phase all PMOS charge pump based on the Pelliconi structure is proposed with high voltage boosting efficiency, strong driving capability and large power efficiency. The proposed charge pump uses a complementary structure to solve the voltage driving problem in the conventional charge pump structures. Two auxiliary substrate switching PMOS transistors are added to mitigate the PMOS body effect. The degradation of the output voltage and power efficiency caused by the high threshold voltage drop of high-voltage transistors is eliminated by means of dynamic gate control structure. The proposed charge pump is implemented in 2Xnm process of 3D V-NAND with all PMOS transistors. The simulation results show that the output voltage of proposed 9 stages charge pump can be reached to 23.24V, and the maximum power efficiency of 82.5% can be achieved with 20uA load current, under 20 MHz clock frequency for a power supply voltage of 3 V.

In this paper, a low‐voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross‐connected NMOS voltage doubler stages. For very low‐voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD‐PMOS) in parallel to the cross‐connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD‐BCLK). Simulations at 50 MHz have shown that a five‐stages charge pump with CVD can achieve a 1.5–8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD‐PMOS and the charge pump with CVD‐BCLK, respectively.

In conventional CMOS charge pump circuits, there are some non-ideal effects such as the clock feedthrough, current mismatch and charge sharing which result in a phase offset in phase-locked loop circuits. This paper presents a new charge pump to reduce the jitter. The proposed and conventional charge pumps are simulated and compared. The circuit is implemented using a 0.35µm mix-signal CMOS process. And the simulation result is obtained by SPECTRES.

A high current driving capability charge pump circuit is proposed. By adopting the dynamic boosting circuit, the overdrive voltages of all the charge transfer switches (CTS's) in the charge pump are maintained for a large loading current. In addition, the largest voltage difference between any of the terminals of all the transistors does not exceed the supply voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , and solves the gate-oxide overstress problem in the conventional charge pump circuits and enhances the reliability. Other advantages of the proposed charge pump include high pumping efficiency because of no threshold voltage drop and 2-phase operation, without the need of extra power consumption on the logic circuits and drivers. The proposed charge pump circuit is designed and simulated based on a low voltage process. Results show that the charge pump can operate in a wide output current range.

In this paper, a new charge pump circuit for reducing charge and discharge currents with low power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump generates maximum 19.9 \(\upmu \)A current. This charge pump is designed and simulated in TSMC 0.18 \(\upmu \)m CMOS technology in order to be used in a delay-locked loop. One of the benefits of this circuit is its capability to be applied in a wide frequency range from 50 to 800 MHz with power consumption range of 410–740 \(\upmu \)W. The proposed charge pump exploits feedback loop in order to achieve suitable current matching and also has a good characteristics in high frequencies.

This paper proposes charge pumps with improved power efficiency suitable for low-power on-chip applications. Undesired charge transfer, which has a direction opposite to that of the intended current flow, presents a significant source of power loss in charge pumps. The proposed charge pump circuit utilizes charge transfer switches with a complementary branch scheme to significantly reduce undesired charge transfer, thereby improving power efficiency and increasing output voltage effectively. An optimized gate control strategy is applied to further decrease the power loss caused by undesired charge transfer. Simulations of 8-stage charge pumps in a $0.13~\mu \text{m}$ standard CMOS technology show that for an input supply voltage of 1.2 V, the proposed charge pump circuit reaches a power efficiency of 58.72% with an output voltage of 7.45 V, when delivering 5-mA load current, and is able to maintain a power efficiency of around 50% and an output voltage of over 5 V as the load current increases to 10 mA. Compared with the other charge pump circuits, the simulation results demonstrate better performance of proposed charge pump circuits in terms of both voltage pumping gain and power efficiency.

A new low voltage charge pump is developed to help start up a step-up converter in energy harvesting applications. The proposed charge pump is the first to utilize both backward control scheme and two branches of charge transfer switches (CTSs) to direct charge flow. The backward control scheme uses the internal boosted voltage to dynamically control the CTSs' gate, and the two branches utilize both NMOS and PMOS to implement their switching structure. The combination of backward control scheme and two-branch operation allows the CTSs to be completely turned on and off. Thus, the reverse charge sharing phenomenon and switching loss are significantly reduced, which effectively improves pumping efficiency. The last stage is specially designed to improve the charge pump's charge and capacitance drivability. Using subthreshold operation and body-bias technique, the charge pump and its clock generator can operate under a low voltage supply. The proposed charge pump circuit is designed in a standard 0.18 $\mu$ m CMOS process. It consists of 6 stages, each with a 24 pF pumping capacitor (total 288 pF pumping capacitance area). Under a 320 mV supply, the measured output voltage of the proposed charge pump can rise from 0 to 2.04 V within 0.1 milliseconds.

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC–DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump's power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.

A new reconfigurable charge pump topology with tunable conversion ratio is proposed. Analysis of this charge pump shows that it is very suitable for solar energy harvesting. Based on the proposed charge pump, a solar energy harvesting system, which delivers optimum harvesting efficiency, is designed. Both the conversion ratio and the switching frequency of the charge pump are tuned to search for the maximum power point of the whole system under different operation environment. Post-layout simulation results show that our system has a higher efficiency than the conventional design. © 2012 IEEE.

An integrated high voltage charge pump circuit utilising intrinsic process features is introduced. It can produce +20 V to +50 V output from a typical 5 V input. The reported charge pumps achieved the highest density and highest output voltages of the industry. Measurements show output ripples of 400 mV for frequencies around 10 MHz and output load of 28 pF. The reported integrated high voltage charge pump circuits was implemented on 0.8 /spl mu/m DALSA semiconductor technology using standard CMOS devices.

The charge pump belongs to the most critical blocks for electromagnetic compatibility (EMC) of low dropout linear regulators (LDO) because of its switching nature. The goal of this paper is to contribute charge pump design practice and a prediction method for the LDO EMC performance already in an early design phase. LDO noise coupling mechanisms are analyzed. EMC aware circuit design includes the choice of low noise architectures, the right switching frequency and noise filtering. The derived simulation method shows very good matching with EMC test results for an LDO with two different charge pumps fabricated in 350nm high-voltage BiCMOS technology. For a realistic prediction of the EMC noise magnitude, a relatively simple simulation setup gives results with <;3dBμV accuracy. A trippler current mode charge pump turned out to be well suitable for EMC. Conducted emissions could be predicted and confirmed to be improved by ~50dBμV versus a conventional voltage mode charge pump.

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V DD = 0.9 V, approximately 10% higher peak power efficiency at V DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.

A fully integrated cross-coupled charge pump circuit with a new clock scheme has been presented in this paper. The new clock scheme ensures that all NMOS pre-charge transistors are turned off when the voltages of main clock signals are high. Notably, all PMOS transfer transistors will be turned off when the voltages of the main clock signals are low. As a result, the charge pump eliminates all of the reversion power loss and reduces the ripple voltage. The proposed charge pump has a better performance even in scenarios where the main clock signals are mismatched. The proposed charge pump circuit was simulated using spectre in the TSMC 0.18 µm CMOS process. The simulation results show that the proposed charge pump circuit has a high voltage conversion efficiency and low ripple voltage.

This paper presents a 2X/1.5X switched-capacitor charge pump for phase change memory (PCM). For a 16-bitparallelism PCM, the set/reset time is more than 100 ns, and the charge pump should output a minimum 60 mA load current. The proposed charge pump can supply 4.1 V voltage and 0-60 mA current for PCM, with an input voltage range of 2.2-3.5 V. It can also automatically change the power conversion ratio between the 2X/1.5X modes according to input voltage. For the improvement of efficiency and load transient response, an auto-adjustable output regulation scheme is employed. In this scheme, two new reference voltages are introduced and compared with output voltage. Average lasting time of the enable signal changes under different load conditions. The Enable signal then controls booster’s power transistors switching to regulate output voltage. In this way, output voltage was controlled within a permissible range. The charge pump has been designed and simulated in a 40nm CMOS process. The results show maximum power efficiency in 30 mA load current is 90.73%, and conversion ratio control increases the efficiency by 23.06% in 3 V.