Charge Pump Circuits for Low‐voltage Applications

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. With the switching substrate technique and boosted transistor, the influence of body effect is almost eliminated and the voltage gain at each pumping node is greatly increased. So higher output voltage and higher efficiency than the conventional charge pump can be obtained by the proposed charge pump. Simulation results of different supply voltages and stage numbers at 2MHz input clock frequency are shown in this paper

In this paper, an improved four-phase all PMOS charge pump based on the Pelliconi structure is proposed with high voltage boosting efficiency, strong driving capability and large power efficiency. The proposed charge pump uses a complementary structure to solve the voltage driving problem in the conventional charge pump structures. Two auxiliary substrate switching PMOS transistors are added to mitigate the PMOS body effect. The degradation of the output voltage and power efficiency caused by the high threshold voltage drop of high-voltage transistors is eliminated by means of dynamic gate control structure. The proposed charge pump is implemented in 2Xnm process of 3D V-NAND with all PMOS transistors. The simulation results show that the output voltage of proposed 9 stages charge pump can be reached to 23.24V, and the maximum power efficiency of 82.5% can be achieved with 20uA load current, under 20 MHz clock frequency for a power supply voltage of 3 V.

An integrated high voltage charge pump circuit utilising intrinsic process features is introduced. It can produce +20 V to +50 V output from a typical 5 V input. The reported charge pumps achieved the highest density and highest output voltages of the industry. Measurements show output ripples of 400 mV for frequencies around 10 MHz and output load of 28 pF. The reported integrated high voltage charge pump circuits was implemented on 0.8 /spl mu/m DALSA semiconductor technology using standard CMOS devices.

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V DD = 0.9 V, approximately 10% higher peak power efficiency at V DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.

This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

This paper proposes a low input voltage charge pump using 0.18um CMOS process for energy harvesting. There are two main sections in the charge pump system: Low Voltage Charge Pump (LVCP) and High Voltage Charge Pump (HVCP). In the LVCP, a negative charge pump is utilized to improve the efficiency at low input voltage, Dynamic Body Bias (DBB) and switch-conductance enhancement techniques are applied to a unit stage of the two-stage charge pump. In the HVCP, the charge pump circuit utilizes charger transfer switches (CTS) with a complementary banch scheme to significantly reduce undesired charge transfer, and an optimized gate control strategy is applied to further decrease the power loss caused by undesired charge transfer. The simulation result demonstrates that the proposed circuit can achieve 97% voltage conversion and drive 800uA load current at 0.6V input voltage. In the region of 0.4V to 0.6V input voltage, the circuit performs well with the load resistance of 10K ohms.

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC–DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump's power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.

This paper presents a CMOS based RF-to-DC converter using a proposed cross-coupled charge pump for energy harvesting. Extraction of high DC voltages from rectifier block in the charge pumps is always a serious bottleneck for RF energy scavenging. One of the dominant obstacles is the threshold voltage (Vth) of the MOS transistor. In this work we are proposing a simple mechanism to eliminate the Vth dependence in MOS transistor, which inherently improves the DC extraction ability of charge pump. The proposed system is implemented in 180nm CMOS technology and simulated using Cadence Spectre. The extracted DC voltage from RF energy is selected as Figure of Merit. It is found using simulation that the modified charge pump shows a high efficiency in DC extraction from RF signal than the conventional cross coupled rectifier based charge pump.

This paper proposes charge pumps with improved power efficiency suitable for low-power on-chip applications. Undesired charge transfer, which has a direction opposite to that of the intended current flow, presents a significant source of power loss in charge pumps. The proposed charge pump circuit utilizes charge transfer switches with a complementary branch scheme to significantly reduce undesired charge transfer, thereby improving power efficiency and increasing output voltage effectively. An optimized gate control strategy is applied to further decrease the power loss caused by undesired charge transfer. Simulations of 8-stage charge pumps in a $0.13~\mu \text{m}$ standard CMOS technology show that for an input supply voltage of 1.2 V, the proposed charge pump circuit reaches a power efficiency of 58.72% with an output voltage of 7.45 V, when delivering 5-mA load current, and is able to maintain a power efficiency of around 50% and an output voltage of over 5 V as the load current increases to 10 mA. Compared with the other charge pump circuits, the simulation results demonstrate better performance of proposed charge pump circuits in terms of both voltage pumping gain and power efficiency.

A low voltage charge pump with high pumping efficiency is proposed in this paper. To get high pumping efficiency, the proposed circuit uses 2 branches cross coupled structure. To eliminate the body effect and threshold voltage drops, PMOS transistors are used as Charge Transfer Switch (CTS). The inverters below and above the CTS PMOS for controlling the gate of CTS PMOS properly. Undesired charge transfer flows higher voltage node voltage to lower voltage node is removed as the NMOS transistor and PMOS transistor below and above the CTS PMOS turn off during the clock transition. Furthermore, the time when those NMOS transistor and PMOS transistor are both off is short and due to the cross coupled wiring, the fast gate control would be able to made by present and previous stage. So that the cross coupled CTS charge pump has higher pumping efficiency than conventional circuits. The simulation results show that the proposed circuit's performance is better than other circuits.

A high current driving capability charge pump circuit is proposed. By adopting the dynamic boosting circuit, the overdrive voltages of all the charge transfer switches (CTS's) in the charge pump are maintained for a large loading current. In addition, the largest voltage difference between any of the terminals of all the transistors does not exceed the supply voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , and solves the gate-oxide overstress problem in the conventional charge pump circuits and enhances the reliability. Other advantages of the proposed charge pump include high pumping efficiency because of no threshold voltage drop and 2-phase operation, without the need of extra power consumption on the logic circuits and drivers. The proposed charge pump circuit is designed and simulated based on a low voltage process. Results show that the charge pump can operate in a wide output current range.

Wide dynamic range active pixel sensor(APS) using a charge pump circuit has been designed by using 2-poly 4-metal <TEX>$0.35{\mu}M$</TEX> standard CMOS technology. The structure of the proposed APS is similar to the structure of the conventional 3-Tr APS. The proposed unit pixel consists of one photodiode and three MOSFETs. Using a charge pump circuit, the dynamic range of the proposed APS is increased, compared to the conventional 3-Tr APS.

This paper aims at investigating some methods for designing an area- and power-efficient Dickson charge pump circuit for on-chip high-voltage source generation. A comprehensive study on two conventional methods, with one of them based on optimizing the number of stage for minimum silicon area (minimum area method) and the other for maximum power efficiency (optimal power method), will be presented by considering both top- and bottom-plate parasitic capacitances. It was found that when the parasitic factors are as large as 0.1, the area and power efficiencies of the charge pumps designed with either the optimal power or minimum area method do not have much degradation. However, when the parasitic factors are small, charge pumps designed with the optimal power and minimum area methods can, respectively, result in a large area and poor power efficiency. The power efficiency of the charge pump designed with the minimum area method may be reduced by 50 %, while the area of the charge pump designed with the optimal power method can be 1---2 times larger, when the parasitic factors are 0.01. Hence, neither the optimal power nor minimum area methods should be used when the parasitic factors are small, unless the power or area is the only concern in the design. With this connection, the number of stage which leads to an area and power-efficient charge pump is suggested. Validity was proved by the good agreement between the simulated and the expected results for some designed charge pump circuits of the proposed design strategy.

Design of low-voltage and efficient energy-harvesting circuits is becoming increasingly important, particularly, for autonomous systems. Since the amount of energy that can be harvested from the surrounding environment is limited, the available output voltage of a harvester is low. Therefore, the design of a low-input-voltage (low-VIN) up-converter is critical to self-powered systems [1-3]. Moreover, the form factor is very constrained in applications such as wearable electronic devices and sensor networks. Recently, low-VIN charge pumps (CPs) for energy harvesting has been compared with DC-DC converters using a large inductor [1-3]. CPs introduced in [1] and [2] use the advanced process technology to push VIN down to the subthreshold region. The CP in [1] introduces a forward-body-biasing (FBB) technique, which improves the voltage conversion efficiency (VCE) for low VIN but shows poor power conversion efficiency (PCE). The CP in [2] achieves the lowest operation voltage. However, the design with a 10-stage CP provides low output power. This paper presents a CP with switching-body-biasing (SBB), adaptive-dead-time (AD), and switch-conductance (SW-G) enhancement techniques to improve the PCE for low VIN as well as to extend the maximum load current.

This paper proposes a new organization of charge pump circuits based on a voltage doubler that takes a DC input and outputs a doubled DC voltage. By cascading n multi-phase voltage doublers (MPVD), the resulting charge pump has the voltage gain equal to 2/sup n/. It needs n clock pairs to control the pumping process, MPVD is a minimum capacitance realization of the switched-capacitor based voltage doubler. An n-stage MPVD needs n+1 capacitors and 2/sup n/ switches. To avoid the short circuit during switching, a dock pairs generator is used to achieve multi-phase non-overlapping clock pairs. A frequency regulator is designed to lower the charging frequency when the load becomes lighter, thus reducing the power loss during switching. A 2-stage MPVD is implemented in the Orbit 2.0 /spl mu/m analog CMOS technology. The simulation results show that the output voltage is 3.995 times the power supply. By using the frequency regulator, the power efficiency is dramatically improved when the load becomes lighter.