High voltage charge pump using standard CMOS technology

This paper proposes a low input voltage charge pump using 0.18um CMOS process for energy harvesting. There are two main sections in the charge pump system: Low Voltage Charge Pump (LVCP) and High Voltage Charge Pump (HVCP). In the LVCP, a negative charge pump is utilized to improve the efficiency at low input voltage, Dynamic Body Bias (DBB) and switch-conductance enhancement techniques are applied to a unit stage of the two-stage charge pump. In the HVCP, the charge pump circuit utilizes charger transfer switches (CTS) with a complementary banch scheme to significantly reduce undesired charge transfer, and an optimized gate control strategy is applied to further decrease the power loss caused by undesired charge transfer. The simulation result demonstrates that the proposed circuit can achieve 97% voltage conversion and drive 800uA load current at 0.6V input voltage. In the region of 0.4V to 0.6V input voltage, the circuit performs well with the load resistance of 10K ohms.

In this paper, a low‐voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross‐connected NMOS voltage doubler stages. For very low‐voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD‐PMOS) in parallel to the cross‐connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD‐BCLK). Simulations at 50 MHz have shown that a five‐stages charge pump with CVD can achieve a 1.5–8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD‐PMOS and the charge pump with CVD‐BCLK, respectively.

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. With the switching substrate technique and boosted transistor, the influence of body effect is almost eliminated and the voltage gain at each pumping node is greatly increased. So higher output voltage and higher efficiency than the conventional charge pump can be obtained by the proposed charge pump. Simulation results of different supply voltages and stage numbers at 2MHz input clock frequency are shown in this paper

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V DD = 0.9 V, approximately 10% higher peak power efficiency at V DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC–DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump's power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.

Design strategies in analyzing important design factors of integrated high voltage charge pump circuits are presented in this paper. By using concrete examples, this paper is supposed to provide a solid understanding of the design constraints during the integrated high voltage charge pump design tasks and to be beneficial for circuit optimization.

This paper presents a fully integrated high voltage charge pump which enables a reconfigurable, energy-efficient multi-band transceiver. Using a high voltage CMOS technology from Austriamicrosystems and a 4-phase charge-pump (DC/DC converter) circuit architecture, up to 120 V supply voltage can be generated from a 3.7 V DC battery using this monolithically integrated circuit. The very small footprint of this solution enables the integration of this multi-band transceiver in mobile devices, whereas the concept of reconfigurability can also be applied to fixed transceiver installations to optimize power efficiency.

This paper presents a novel NMOS-based switching cell architecture specially developed for semicustom smart power ICs that can be implemented even using low cost, standard CMOS technologies. This approach is highly suitable either for cost effective smart power ICs or for discrete high power devices, since the NMOS transistor cell can be used to implement medium power switches or intermediate interface stages. This work also presents an overview on integration strategies and layout considerations, using different widely available processes of standard low cost CMOS technology, with no extra processing steps. Optimized NMOS devices were associated in special structures in a matrix arrangement, conveniently designed to be easily programmed using top metal masks, according to the required functionality, in order to implement topologies for commutation, drive, protection, amplification, sensing and control, capable to handle high voltage signals. The proposed power array allows the fast prototyping of a wide range of applications. As an example a therapeutic stimulation microsystem was obtained through the configuration of this power array fabricated using a standard CMOS technology. A boost converter was implemented as the actuator. Experimental results are presented and overall performance is discussed. These strategies can be extended to smart power and other power integration dedicated technologies, when customized ICs are in scope, to reduce low series production cost and production cycle.

This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

In this paper, an improved four-phase all PMOS charge pump based on the Pelliconi structure is proposed with high voltage boosting efficiency, strong driving capability and large power efficiency. The proposed charge pump uses a complementary structure to solve the voltage driving problem in the conventional charge pump structures. Two auxiliary substrate switching PMOS transistors are added to mitigate the PMOS body effect. The degradation of the output voltage and power efficiency caused by the high threshold voltage drop of high-voltage transistors is eliminated by means of dynamic gate control structure. The proposed charge pump is implemented in 2Xnm process of 3D V-NAND with all PMOS transistors. The simulation results show that the output voltage of proposed 9 stages charge pump can be reached to 23.24V, and the maximum power efficiency of 82.5% can be achieved with 20uA load current, under 20 MHz clock frequency for a power supply voltage of 3 V.

Wide dynamic range active pixel sensor(APS) using a charge pump circuit has been designed by using 2-poly 4-metal <TEX>$0.35{\mu}M$</TEX> standard CMOS technology. The structure of the proposed APS is similar to the structure of the conventional 3-Tr APS. The proposed unit pixel consists of one photodiode and three MOSFETs. Using a charge pump circuit, the dynamic range of the proposed APS is increased, compared to the conventional 3-Tr APS.

This paper reports a novel 0.8 V content addressable memory (CAM) cell circuit with a fast tag-compare capability using the bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology following the SOI DTMOS technology for low-voltage VLSI systems. Using four PMOS devices with their body controlled dynamically in the tag-compare portion, this CAM cell, which is built in standard bulk CMOS technology using the BP-DTMOS technique, has a faster tag-compare operation at a supply voltage of 0.8 V as compared to the one not using the BP-DTMOS technique.

Color recognition sensor in standard CMOS technology

The mmW and sub-THz frequency bands hold enormous potential for high-speed multi-Gb/s communications as well as sensing and imaging applications. With the tremendous leap in the operating frequencies with scaling, CMOS becomes the technology of choice for highly integrated solutions for many of these applications, enabling smaller size, lower power consumption and lower cost. This paper will focus on the recent developments in radio architectures for gigabit wireless communication, radars and gas sensing in the 60 GHz, 77 GHz and 180-300 GHz bands using standard digital CMOS technology. The authors will present a 200 GHz receiver front-end designed in a standard CMOS technology along with injection-locking based frequency generation schemes at mmW and THz frequencies.

A regulated multiple-output high-voltage charge pump IC for implantable neural stimulators