An improved VLSI architecture for Viterbi decoder

The Viterbi algorithm is widely applied to problems of the state estimation of a finite-state discrete-time Markov process, such as convolutional and trellis decoding. Although conventional Viterbi decoders process all states concurrently, the sequential nature of this algorithm limits the decoding throughput for a given integrated circuit technology and thereby restricts its applications. This paper presents the architecture of a single-chip Viterbi decoder combining two methods to speed-up the data rate: the "radix" trellis method and the interleaved method. The resulting architecture is very attractive for applications where high-speed decoding is essential, such as satellite digital communication systems.

Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.

Low-power microarchitecture designs of Viterbi decoder are considered one of the on-demanding issues in Very Large-Scale Integration (VLSI). Viterbi decoders consume 35% of the power and 76% of the complexity in digital communication schemes, e.g., IEEE 802.11 a/g WLAN schemes. Development of Viterbi decoder itself reduces dramatically system complexity; the decoder has a source of power sink unit which rises in Add Compare-Select (ACS) unit. Various levels of development exist in VLSI such as architecture, microarchitecture, circuit, and transistor. ACS is structured of adder, comparator, and selector, so microarchitecture development of ACS unit intends one of these superior blocks. Adders in VLSI designs have a tremendous interest as they are the kernel of any digital system so enhancing this basic building block, which is used over and over, influences system specification. This paper targets different microarchitectural approaches to shrink the power of this unit which enhances overall system specification. Microarchitecture development encompasses using another block instead of the existing one or repositioning current blocks. In this review paper, comparisons of different parallel adders are presented to achieve low consumption power while obtaining high-speed operation of the addition, and an arrangement of ACS blocks to reduce the complexity of the decoder is also provided.

Sn area efficient high speed Veterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code is proposed By replacing each delay (or storage) element in state metrics memory (or path metrics memory) and path memory (or survival memory) with I delays, interleaved Viterbi decoder is obtained. The speed of this decoder architecture is as fast as the operating clock speed. The latency of proposed interleaved Viterbi decoder is decoding depth (DD) /spl times/ interleaving degree (I)', which is linearly increased with the interleaving degree I.

A runtime reconfigurable architecture for high speed Viterbi and turbo decoding is designed and implemented on an FPGA. The architecture can be reconfigured to decode a range of convolutionally coded data with constraint lengths varying from 3 to 9, rates 1/2 and 1/3, and various generator polynomials. It can also be reconfigured to decode turbo coded data with constraint length 4 and rate 1/3. Reconfiguration of the architecture requires a single clock cycle and does not require FPGA reprogramming. The proposed architecture can deliver data rates up to 60.5 Mbit/s for Viterbi decoding and 3.54 Mbit/s for turbo decoding, making it suitable for a range of wireless communication standards like IEEE 802.11a, 3GPP, GSM, GPRS, and many others.

A high-speed and area-efficient Viterbi decoder is presented in the paper, and a new survivor path structure including RAM blocks and trace-back decode circuit is proposed. The survivor path memory is consist of 4 single-port RAM blocks, which reduces the chip's area comparing to the dual-port RAM structure; and a simple trace-back decoder circuit is implemented to get high speed. Only 2300 LEs are used in the Altera Stratix FPGA device to implement this design, and its speed is up to 163 MHz. The proposed Viterbi decoder can be introduced to the digital communication systems that need high speed such as DTV or HDTV broadcast

The control logic of the modern Full Authority Digital Engine Control (FADEC) is comprised of many control loops, each of which has a specific purpose. Typical control loops include (but are not limited to) a high or low rotor speed governor, an Acceleration and Deceleration loop, and various limiting loops for temperature, speed, fuel flow, and rate of change of fuel flow. The logic that determines which of these loops is “in control” at any particular time has a history of being very simplistic. This Selection Logic is usually nothing more that a cascade of minimum and maximum selection logic gates. Since this logic is so simplistic, the control engineer often has to “fine tune” the compensator design for each loop, in order to achieve proper performance. The purpose of this paper is to a present a means of achieving a selection logic design based on Fuzzy Logic principles. Hereafter, this shall be referred to as a Fuzzy Fuel Flow Selector. The paper provides a brief overview of the most typical architecture for real time embedded FADEC control logic, rule development for the Fuzzy Fuel Flow Selector, and a realistic implementation of the Fuzzy Fuel Flow Selector. Also provided is a typical application that is used to contrast the performance between traditional selection logic and the Fuzzy Fuel Flow Selector. An overview of the Fuzzy Logic process is also included for completeness.

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

A parallelisation algorithm of decoding convolutional codes with the Viterbi algorithm is presented. The architecture of parallel decoding analysed here suits the VLSI realisation very well and allows high-speed decoding.

This paper presents a new algorithm on lower-power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. It results in increasing the area of spurious switching activity region, and further reducing the switching activity with gated-clocks during trace-back operation. With the SYNOPSYS power estimation tool, DesignPower, our experimental result shows on the average 40% reduction in power with the same latency at a cost of 23% increase in area against the trace-back unit introduced by Truong et al. (1992). The proposed survivor memory scheme can be applied to the digital communication systems for targeting low power consumption.

Software defined radio adapts various modulation schemes, encoding techniques by changing its configuration. It has earned great attention in the recent years for its flexibility to adapt various techniques without the need of replacement of the existing hardware. SDR reduces the cost complexity and provides the flexible communication system. This paper presents the viterbi decoder architecture with improved trace back unit for a code rate of 1/2 and a constraint length of k = 3. This decoder finds advantages in software defined radio applications due to its area efficiency and speed. The proposed decoder is simulated in Xilinx 14.1 and implemented in a field programmable gate array (FPGA).

Dynamic partial reconfigurable Viterbi decoder for wireless standards

Quality of service (QoS) is one of the most important factors in mobile communication networks. Decreasing of delay, including processing time, and error correction are proposed to get higher QoS in mobile networks. Reed-Solomon coding is one of the most important schemes for this purpose, for error correction. In this paper a pipeline approach of RS decoder is proposed to reduce the processing time. In the pipeline architecture of Reed-Solomon decoder two schemes are proposed, first the Reed-Solomon decoder is developed in five stages pipeline, then to reduce the data dependencies between stages, it is developed by three stages pipeline. Because of the data dependency between the stages, it is impossible to achieve ideal speedup. In the five-stage pipeline scheme of RS decoder the data dependency has been caused the %18.5 loss in the speedup, this value for the three-stage pipeline scheme is about %14. The hardware description language (HDL) method is employed to hardware synthesis the Reed-Solomon decoder on FPGA chips.

A high-speed, emitter-coupled logic (ECL) gate array which greatly facilitates the implementation of very high-speed Viterbi algorithm processors has been developed. These high-speed Viterbi decoders were incorporated into two bandwidth-efficient, jointly optimized coded modulation systems with baseband information rates of 140 and 200 Mbit/s. The 200-Mb/s system was developed for NASA under the Advanced Modulation Technology Development program. The octal phase shift keying (8PSK) modulation technique used in these systems requires symbol rates of 60 to 75 Msymbol/s. The gate array device also has the potential for use in similar systems with symbol rates in excess of 100 Msymbol/s. Some details of the coded modulation systems that require the implementation of high-speed Viterbi processors are provided to demonstrate current practical applications and the need for this processing capability. The specific gate array design is described in conjunction with the performance goals and measured parameters of the completed device. >

Trellis codes and rate-k/n convolutional codes are often used in wired communications, terrestrial radio and satellite radio links for bandwidth efficiency. To further increase data rates and coding gain, higher rate codes with more states can be used. Cost effectiveness of decoders for these complex rate-k/n and trellis codes becomes a major issue. While cost effective decoder architectures for rate-k/n convolutional codes and high speed decoder architectures are well know, current low-cost decoders for rate-k/n convolutional and trellis codes still resort to suboptimal decoding algorithms. This paper describes a new way to design cost-effective Viterbi decoders for complex rate-k/n convolutional and trellis codes through a co-design of state-processor mapping, topology scaling, scheduling, metric reordering, and VLSI structures of processing elements. Also proposed is a new processing element which has 1/(2/sup k/-1) of the complexity of a conventional processing element.