Parallel architecture for high-speed Viterbi decoding of convolutional codes

The Viterbi algorithm is widely applied to problems of the state estimation of a finite-state discrete-time Markov process, such as convolutional and trellis decoding. Although conventional Viterbi decoders process all states concurrently, the sequential nature of this algorithm limits the decoding throughput for a given integrated circuit technology and thereby restricts its applications. This paper presents the architecture of a single-chip Viterbi decoder combining two methods to speed-up the data rate: the "radix" trellis method and the interleaved method. The resulting architecture is very attractive for applications where high-speed decoding is essential, such as satellite digital communication systems.

We introduce the notion of innovations for Viterbi decoding of convolutional codes. First, we define a kind of innovation corresponding to the received data, i.e., the input to a Viterbi decoder. Then, the structure of a scarce-state-transition (SST) Viterbi decoder is derived in a natural manner. It is shown that the newly defined innovation is just the input to the main decoder in an SST Viterbi decoder and generates the same syndrome as the original received data does. A similar result holds for quick-look-in codes as well. In this case, however, the precise innovation is not defined. We see that this innovation-like quantity is related to the linear smoothed estimate of the information. The essence of innovations approach to a linear filtering problem is first to whiten the observed data, and then to treat the resulting simpler white-noise observations problem. In our case, this corresponds to the reduction of decoding complexity in the main decoder in an SST Viterbi decoder. We show that the distributions related to the main decoder (i.e., the input distribution and the state distribution in the code trellis for the main decoder) are much biased under moderately noisy conditions. We see that these biased distributions actually lead to the complexity reduction in the main decoder. Furthermore, it is shown that the proposed innovations approach can be extended to maximum-likelihood decoding of block codes as well.

In this paper, we propose a parallel block-based Viterbi decoder (PBVD) on the graphic processing unit (GPU) platform for the decoding of convolutional codes. The decoding procedure is simplified and parallelized, and the characteristic of the trellis is exploited to reduce the metric computation. Based on the compute unified device architecture (CUDA), two kernels with different parallelism are designed to map two decoding phases. Moreover, the optimal design of data structures for several kinds of intermediate information are presented, to improve the efficiency of internal memory transactions. Experimental results demonstrate that the proposed decoder achieves high throughput of 598Mbps on NVIDIA GTX580 and 1802Mbps on GTX980 for the 64-state convolutional code, which are 1.5 times speedup compared to the existing fastest works on GPUs.

Compared with the Viterbi algorithm, the stack algorithm can provide lower hardware complexity, especially for long constraint length convolutional codes. This paper proposes a fast and simple hardware stack sequence decoder with an efficient state scheme. The stack decoder structure is mainly composed of RAM and shift register, and three independent RAM parts store the path metric, node, and encoder state of each path. Accessing different data items of the same stack in the data structure can be achieved by addressing the RAM with the same register value. In the decoding process, the paths are sorted according to the rules of the stack algorithm, and the path located at the top of the stack will execute the state of path extension in the next clock cycle. In this paper, an FPGA prototype of the stack decoder is constructed, and high-speed decoding is obtained by optimizing the state scheme, avoiding additional time-consuming read/write operations.

An improved VLSI architecture for a high-speed Viterbi decoder is proposed. We partitioned the datapath of the Viterbi decoder into largely 3 pipeline stages and to reduce the operation overhead of the add-compare-select unit (ACSU), removed the minimum metric selection logic and exploited the constant subtraction scheme for the metric rescaling. This can be done by using unsigned arithmetic and the overflow detection unit. We also discussed the uselessness of the minimum metric selection logic in the analysis of truncation effects. Simulation results demonstrated that if the traceback depth is long enough, the arbitrary state decoding can be used without many disadvantages over the best state decoding. The survival memory unit (SMU) pipelining architecture based on the modified traceback algorithm is also presented. By exploiting the two registers and multiplexers, we made a one-stage pipeline cell and by cascading them, a traceback operation without LIFO or a complex memory controller can be achieved with a latency of only 2T.

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

In 1995, Best etal. published a formula for the exact bit error probability for Viterbi decoding of the rate R =1/2, memory m = 1 (two-state) convolutional encoder with generator matrix G(D) = (1 1 + D) when used to communicate over the binary symmetric channel. Their formula was later extended to the rate R = 1/2, memory m = 2 (four-state) convolutional encoder with generator matrix G(D) = (1 + D2 1 + D + D2) by Lentmaier et al. In this paper, a different approach to derive the exact bit error probability is described. A general recurrent matrix equation, connecting the average information weight at the current and previous states of a trellis section of the Viterbi decoder, is derived and solved. The general solution of this matrix equation yields a closed-form expression for the exact bit error probability. As special cases, the expressions obtained by Best et al. for the two-state encoder and by Lentmaier et al. for a four-state encoder are used. The closed-form expression derived in this paper is evaluated for various realizations of encoders, including rate R = 1/2 and R = 2/3 encoders, of as many as 16 states. Moreover, it is shown that it is straightforward to extend the approach to communication over the quantized additive white Gaussian noise channel.

It has been demonstrated that turbo codes substantially outperform other codes, e.g., convolutional codes, both in the non-fading additive white Gaussian noise (AWGN) channel as well as multiple-transmit and multiple-receive antenna fading channels. Moreover, it has also been reported that turbo codes perform very well in fast fading channels, but perform somewhat poorly on slow and block fading channels of which the broadband fixed wireless access (FWA) channel is an example. In this paper, we thoroughly compare the performance of turbo-coded and convolutional-coded broadband FWA systems both with and without antenna diversity under the condition of identical complexity for a variety of decoding algorithms. In particular, we derive mathematical expressions to characterize the complexity of turbo decoding based on state-of-the-art Log-MAP and Max-Log-MAP algorithms as well as convolutional decoding based on the Viterbi algorithm in terms of the number of equivalent addition operations. Simulation results show that turbo codes do not offer any performance advantage over convolutional codes in FWA systems without antenna diversity or FWA systems with limited antenna diversity. Indeed, turbo codes only outperform convolutional codes in FWA systems having significant antenna diversity.

A high-speed and area-efficient Viterbi decoder is presented in the paper, and a new survivor path structure including RAM blocks and trace-back decode circuit is proposed. The survivor path memory is consist of 4 single-port RAM blocks, which reduces the chip's area comparing to the dual-port RAM structure; and a simple trace-back decoder circuit is implemented to get high speed. Only 2300 LEs are used in the Altera Stratix FPGA device to implement this design, and its speed is up to 163 MHz. The proposed Viterbi decoder can be introduced to the digital communication systems that need high speed such as DTV or HDTV broadcast

Trellis codes and rate-k/n convolutional codes are often used in wired communications, terrestrial radio and satellite radio links for bandwidth efficiency. To further increase data rates and coding gain, higher rate codes with more states can be used. Cost effectiveness of decoders for these complex rate-k/n and trellis codes becomes a major issue. While cost effective decoder architectures for rate-k/n convolutional codes and high speed decoder architectures are well know, current low-cost decoders for rate-k/n convolutional and trellis codes still resort to suboptimal decoding algorithms. This paper describes a new way to design cost-effective Viterbi decoders for complex rate-k/n convolutional and trellis codes through a co-design of state-processor mapping, topology scaling, scheduling, metric reordering, and VLSI structures of processing elements. Also proposed is a new processing element which has 1/(2/sup k/-1) of the complexity of a conventional processing element.

The author provides an overview of various key features of De Bruijn graph-based VLSI architectures. The advantages of De Bruijn architectures over such other architectures as cube and shuffle-exchange are discussed. Important differences between De Bruijn interconnects and others are also described. The evolution of the De Bruijn interconnect is described. The FFT architecture and the Viterbi decoder for convolutional codes are examined in detail. The issues of routing and fault tolerance are addressed. >

In this work, anew approach of designing channel codes for partial band interference channels based on hidden puncturing is introduced that is not requiring explicit estimation of the interferer. We investigate the performance of specially designed rate 1/2 Viterbi decoding of convolutional codes and rate 1/2 turbo codes in an example scenario with partial band FM interference. We show by means of simulations that for Gaussian as well as for a variety of multipath fading profiles, a significant channel coding gain compared to a conventional system can be achieved. Thereby the performance of optimal combining, that is requiring optimal estimation of the interferer, can be approached very closely in various scenarios.

Papílio is a Feistel cipher encryption algorithm where the coder process (function F) is based in the Viterbi algorithm. The Viterbi algorithm was proposed as a solution to decode convolutional codes. There are several parameters that define the convolution code and Viterbi algorithm; one of them is the generator polynomial. To use Viterbi algorithm in cryptography, it is necessary to make some modifications. The proposed one does not depend on the parameters of Viterbi nor on the parameters of convolution. In this work we will analyze the cryptographic indices (avalanche, diffusion and confusion) of Papílio considering all possible different polynomials and fix the other parameters.KeywordsForward Error CorrectionConvolutional CodeBijective FunctionViterbi AlgorithmText BlockThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

ABSTRACTA Viterbi algorithm (VA) is the optimal decoding strategy for the convolutional code. The Viterbi algorithm is complex and requires a large memory and delay. In this paper, an alternative sub‐optimal decoder based on the artificial neural network (ANN) is proposed and studied using a sliding block decoding algorithm. The ANN is trained in a supervised manner and the system parameters are optimised using computer simulations for the optimum performance. Comparative study with the Viterbi decoder is carried out. The performance of the ANN decoder is found to be comparable to the Viterbi ‘soft’ decoding with much reduced decoding length. The key advantages of the proposed ANN decoder compared with other ANN decoders are the reduced decoding and training length, adaptive decoding, no iteration required and possibility of parallel decoding. Copyright © 2012 John Wiley & Sons, Ltd.

Viterbi decoding is a path maximum-likehood decoding algorithm widely used in modems and error correction devices. The Levenshtein distance has been postulated to be a suitable branch comparison metric for the Viterbi algorithm on channels not only with substitution errors, but also with insertion/deletion errors. However, to a large extent, this hypothesis has still to be investigated. Pruned convolutional codes are constructed by periodically deleting branches in a high rate convolutional code trellis diagram to create a time varying code. The application of rate compatible pruned codes to hybrid ARQ/FEC schemes is proposed here for channels with insertion, deletion and substitution errors. A new type of Viterbi algorithm based on the Levenshtein distance metric is used as the decoding algorithm. Our experiments give evidence that the Viterbi algorithm with the Levenshtein distance metric is suitable as a decoder on channels with both substitution errors and insertion/deletion errors, and furthermore that rate-compatible pruned codes can improve the performance of the decoding