Adaptive ‘soft’ sliding block decoding of convolutional code using the artificial neural network

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

This paper presents a parallel computing approach that is employed to reconstruct original information bits from a non-recursive convolutional codeword in noise, with the goal of reducing the decoding latency without compromising the performance. This goal is achieved by means of cutting a received codeword into a number of sub-codewords (SCWs) and feeding them into a two-stage decoder. At the first stage, SCWs are decoded in parallel using the Viterbi algorithm or equivalently the brute force algorithm. Major challenge arises when determining the initial state of the trellis diagram for each SCW, which is uncertain except for the first one; and such results in multiple decoding outcomes for every SCW. To eliminate or more precisely exploit the uncertainty, an Euclidean-distance minimization algorithm is employed to merge neighboring SCWs; and this is called the merging stage, which can also run in parallel. Our work reveals that the proposed two-stage decoder is optimal and has its latency growing logarithmically, instead of linearly as for the Viterbi algorithm, with respect to the codeword length. Moreover, it is shown that the decoding latency can be further reduced by employing artificial neural networks for the SCW decoding. Computer simulations are conducted for two typical convolutional codes, and the results confirm our theoretical analysis.

Viterbi decoding is a path maximum-likehood decoding algorithm widely used in modems and error correction devices. The Levenshtein distance has been postulated to be a suitable branch comparison metric for the Viterbi algorithm on channels not only with substitution errors, but also with insertion/deletion errors. However, to a large extent, this hypothesis has still to be investigated. Pruned convolutional codes are constructed by periodically deleting branches in a high rate convolutional code trellis diagram to create a time varying code. The application of rate compatible pruned codes to hybrid ARQ/FEC schemes is proposed here for channels with insertion, deletion and substitution errors. A new type of Viterbi algorithm based on the Levenshtein distance metric is used as the decoding algorithm. Our experiments give evidence that the Viterbi algorithm with the Levenshtein distance metric is suitable as a decoder on channels with both substitution errors and insertion/deletion errors, and furthermore that rate-compatible pruned codes can improve the performance of the decoding

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the minimized method (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 /spl mu/ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude.

A new random-error-correction code presented here is one of the most efficient two-error-correction codes. The new code can correct 2-bit random errors within twelve (12) consecutive bits while (15,7) BCH code [1] corrects two errors within fifteen (15) bits and Hagelbarger's code [2] corrects two errors within fourteen (14) bits. Although Peterson and Weldon's double-error-correcting (12,6) code [1] and Massey's two-error-correcting convolutional code [3] also correct two errors within twelve (12) bits, both codes propagate errors. The (12,6) Viterbi code [1], [4] corrects two errors and uses a Viterbi decoder, while the new code is decodable with a one-step majority logic. Error propagation in the feedback majority logic decoder is discussed, and it is proved empirically that the new code presented here does not propagate errors.

A new class of convolutional codes, called skew convolutional codes, that extends the class of classical fixed convolutional codes, is proposed. Skew convolutional codes can be represented as periodic time-varying convolutional codes but have a description as compact as fixed convolutional codes. Designs of generator and parity check matrices, encoders, and code trellises for skew convolutional codes and their duals are shown. For memoryless channels, one can apply Viterbi or BCJR decoding algorithms, or a dualized BCJR algorithm, to decode skew convolutional codes.

It has been demonstrated that turbo codes substantially outperform other codes, e.g., convolutional codes, both in the non-fading additive white Gaussian noise (AWGN) channel as well as multiple-transmit and multiple-receive antenna fading channels. Moreover, it has also been reported that turbo codes perform very well in fast fading channels, but perform somewhat poorly on slow and block fading channels of which the broadband fixed wireless access (FWA) channel is an example. In this paper, we thoroughly compare the performance of turbo-coded and convolutional-coded broadband FWA systems both with and without antenna diversity under the condition of identical complexity for a variety of decoding algorithms. In particular, we derive mathematical expressions to characterize the complexity of turbo decoding based on state-of-the-art Log-MAP and Max-Log-MAP algorithms as well as convolutional decoding based on the Viterbi algorithm in terms of the number of equivalent addition operations. Simulation results show that turbo codes do not offer any performance advantage over convolutional codes in FWA systems without antenna diversity or FWA systems with limited antenna diversity. Indeed, turbo codes only outperform convolutional codes in FWA systems having significant antenna diversity.

In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware.

Papílio is a Feistel cipher encryption algorithm where the coder process (function F) is based in the Viterbi algorithm. The Viterbi algorithm was proposed as a solution to decode convolutional codes. There are several parameters that define the convolution code and Viterbi algorithm; one of them is the generator polynomial. To use Viterbi algorithm in cryptography, it is necessary to make some modifications. The proposed one does not depend on the parameters of Viterbi nor on the parameters of convolution. In this work we will analyze the cryptographic indices (avalanche, diffusion and confusion) of Papílio considering all possible different polynomials and fix the other parameters.KeywordsForward Error CorrectionConvolutional CodeBijective FunctionViterbi AlgorithmText BlockThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Since 1967, Viterbi decoder is considered to be the maximum-likelihood decoding algorithm for convolutional codes and codes with state machine representation. Distance-preserving mapping codes designed from the mapping of convolutional codes outputs to permutation sequences make use of constructions that help choosing the best mapping and improving the performance of Viterbi decoding by improving the distances metrics in the trellis diagram of the code. Combining these new designed codes with M-FSK modulation is to combat permanent frequency disturbances in power-line communications channel. The choice of the M-FSK detector also plays a role in the improvement of the decoding process at the demodulator. Viterbi's ratio Threshold test (VRTT) is modified to avoid the erasure detection, as we are not interested in such errors in our channel and to be considered as a soft decision detection for the envelope detector.

Side-match vector quantization is a finite-state technique for image coding. This research shows that the side-match vector quantization is an error-propagating code and it is similar to a catastrophic convolutional code. Here, we propose a Viterbi-based algorithm to solve this problem. Various noise detection algorithms are integrated into the Viterbi algorithm (to yield the Viterbi-based algorithm) for a much better performance. According to the simulation of a binary symmetric channel with random bit-error rate (BER) 0.1%-0.01%, the Viterbi-based algorithm provides 2.8-9.6 dB and 2.3-8.4 dB gain compared with the conventional side-match vector quantization decoder and the Viterbi decoder, respectively. In addition, the proposed algorithm requires much fewer computations than the Viterbi algorithm.

The puncturing technique allows obtaining high-rate convolutional codes from low-rate convolutional codes used as mother codes. This technique has been successfully applied to generate good high-rate convolutional codes which are suitable for Viterbi and sequential decoding. In this paper, we investigate the puncturing technique for convolutional self-doubly orthogonal codes (CSO/sup 2/C) which are decoded using an iterative threshold-decoding algorithm. Based on an analysis of iterative threshold decoding of the rate-R=b/(b+1) punctured systematic CSO/sup 2/C, the required properties of the rate-R=1/2 systematic convolutional codes (SCCs) used as mother codes are derived. From this analysis, it is shown that there is no need for the punctured mother codes to respect all the required conditions, in order to maintain the double orthogonality at the second iteration step of the iterative threshold-decoding algorithm. The results of the search for the appropriate rate-R=1/2 SCCs used as mother codes to yield a large number of punctured codes of rates 2/3/spl les/R/spl les/6/7 are presented, and some of their error performances evaluated.

A Viterbi decoding algorithm with a scarce-state transition-type circuit configuration, namely the probability selecting states (PSS) mode decoder, is presented. The algorithm has reduced complexity compared to a conventional Viterbi decoder. It is shown that this method has three advantages over the general Viterbi algorithm: it is suitable to the quick look-in code, it applies the optimum decoding in a PSS-type decoder, and it makes full use of the likelihood concentration property. The bit-error-rate (BER) performance of a r=1/2, k=7 (147,135) code and PSS-type Viterbi decoder approximates the optimum performance of the standard Viterbi decoder and reduces the hardware of the conventional Viterbi decoder to about half.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In modern high-speed telecommunication systems a direct analog approach enables the A/D converter to be excluded from the Viterbi decoder implementation and avoids the speed bottlenecks in digital computation. The differential structure eliminates the need for the conventional trace-back memory thus enabling on-line decoding after initial transitional stages. This paper presents the circuit level analysis of branch metric calculation and decision units for a differential analog Viterbi decoder addressed to a (2,1,7) convolutional code. The speed and power consumption in these units is simulated with 0.13 mum CMOS technology. Further, the impact of inaccuracies in these units on the decoder performance is estimated.

In this paper, the design and FPGA implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the adaptive Viterbi algorithm is used. A scheme for providing a tolerance to clock-to-data skew to avoid timing violation is proposed. A process of eliminating spurious toggles, for reducing power consumption, is also developed. It is shown that the total power consumption in the implementation of the adaptive algorithm can be reduced by up to 43% compared to that in the implementation of a corresponding non-adaptive Viterbi algorithm, with a negligible increase in the hardware.