Viterbi-based algorithm for side-match vector quantization over noisy channels

Side-Match Vector Quantization for Reconstruction of Lost Blocks

Side-match vector quantization is an attractive finite-state coding technique for images. This research shows that the side-match vector quantization is similar to catastrophic code where infinite number of decoding errors is caused by a finite number of channel errors. A 1D side- match vector quantization is first proposed to limit the error propagation across different row of blocks when the channel is noisy. Then three tests are proposed for noisy rows detection with minimum overhead information. These tests include the 1D side-match vector quantization decoding test, double-row test, and triple-row test. Finally, a modified Viterbi algorithm is proposed to decode the images encoded by the 1D side-match vector quantization.

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

Rapidly growing demand for high data rates in wireless communication systems is the cause of the merging of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) techniques. MIMO-OFDM technique needs Radio Frequency (RF) front end in each antenna, which is not effective for large dimensional antenna size. Therefore, RF front end on the receiver side will be simplified using a single RF technique based on the Electrically Steerable Parasitic Array Radiator (ESPAR) antenna. In real life, a channel cannot be ideal. Therefore, before the signal is transmitted, that signal must be coded to minimized errors when the data transmission process. Convolutional code is a coding technique that can detect and correct error bit (error control coding) and that it is expected to reduce the quantity of Bit Error Rate (BER). In this research, a simulation is designed to analyze single RF performance on the MIMO-OFDM system using Vertical Bell Laboratories Space-Time (VBLAST) detection for convolutional code encoder and Viterbi decoder. The result simulation shows that the channel estimation technique works well on the MIMO-OFDM system using single RF, which is shown in the magnitude and phase curves against the subcarrier index between the theory channel and the estimated channel are at almost the same points. VBLAST-ZF detector performance is shown in the BER curve against SNR, where the difference BER value for SNR value 10 dB between the theory channel and the estimated channel is 0.001499. Channel coding technique using convolutional code encoder and Viterbi decoder with a rate of ½ works well on the MIMO-OFDM system using single RF which is shown in the BER curve against SNR, where BER value with coding technique is smaller than BER value without coding technique.

Todays need is for increased content and bandwidth to drive communication systems, error control coding has a great demand. To maintain high reliable data and to improve the Bit Error Rate (BER), error correction technique like the Viterbi algorithm is one of the promising solutions. Though it is useful for error correction it dissipates large power. A lot many researches were carried out at architectural as well as algorithmic level to optimize the ACS (Add compare and Select) unit and Survival Memory Management in Synchronous Viterbi Decoders. But still there is a problem of power dissipation which requires more technical solutions. Due to requirements of high speed, low power, low weight and long battery life a low power Viterbi decoders has a great demand in the communication field. This paper proposed the method for survivor path storage and decoding as Minimum Transition Hybrid Register Exchange Method along with handshaking protocol as Level Encoded dual rail (LEDR) encoding to make the system asynchronous. The whole system has been designed on algorithmic level and Simulation is done on Xilinx Tool for Asynchronous Viterbi Decoder using MTHREM.

A novel algorithm for decoding a general rate K/N convolutional code based on recurrent neural network (RNN) is described and analysed. The algorithm is introduced by outlining the mathematical models of the encoder and decoder. A number of strategies for optimising the iterative decoding process are proposed, and a simulator was also designed in order to compare the Bit Error Rate (BER) performance of the RNN decoder with the conventional decoder that is based on Viterbi Algorithm (VA). The simulation results show that this novel algorithm can achieve the same bit error rate and has a lower decoding complexity. Most importantly this algorithm allows parallel signal processing, which increases the decoding speed and accommodates higher data rate transmission. These characteristics are inherited from a neural network structure of the decoder and the iterative nature of the algorithm, that outperform the conventional VA algorithm.

A chaos-based multi-user time division multiplexing (TDM) communication system has been proposed and its benchmark performance compared to that of the chaos-based direct sequence code division multiple access (DS-CDMA) system in the noisy and Rayleigh fading channels. The benchmark performance of the systems is investigated in terms of the bit error rate (BER) under the assumption of perfect synchronisation. The chaotic spreading signals, used to encrypt the binary messages, are generated using the logistic map. The degradation in performance of the systems in the Rayleigh fading channel when compared with the noisy channel is demonstrated. Furthermore, it is shown that in both noisy and Rayleigh fading channels, the chaos-based multi-user TDM system outperforms the chaos-based DS-CDMA system for a large number of users in the system, whereas the chaos-based DS-CDMA system yields better performance for low user numbers. The overall BER performance degradation for the chaos-based DS-CDMA multi-user system in noisy and Rayleigh fading channels is characterised by the flattening of the BER curves at low levels of noise due to the prevailing effects of the interuser interferences.

Recently, vector quantization has become noted as a highly efficient coding method of image and voice data. So far, many of the highly efficient coding problems, or service coding problems, have been studied separately from channel coding problems. This paper reconsiders vector quantization jointly optimizing source coding and channel coding, and proposes a new vector quantizer for noisy channels. Vector quantizers for binary symmetric channels are designed for memoryless Gaussian source, Gauss‐Markov source and the real images, and are compared with the conventional vector quantizer which does not take account of channel errors. As a result, it is shown that the performance of the proposed vector quantizer is improved without adding the redundancy for error correction, and the improvement of the performance of the proposed vector quantizer for noisy channels over the conventional vector quantizer becomes significant for highly correlated sources and longer block length.

A Viterbi decoding algorithm with a scarce-state transition-type circuit configuration, namely the probability selecting states (PSS) mode decoder, is presented. The algorithm has reduced complexity compared to a conventional Viterbi decoder. It is shown that this method has three advantages over the general Viterbi algorithm: it is suitable to the quick look-in code, it applies the optimum decoding in a PSS-type decoder, and it makes full use of the likelihood concentration property. The bit-error-rate (BER) performance of a r=1/2, k=7 (147,135) code and PSS-type Viterbi decoder approximates the optimum performance of the standard Viterbi decoder and reduces the hardware of the conventional Viterbi decoder to about half.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

ABSTRACTA Viterbi algorithm (VA) is the optimal decoding strategy for the convolutional code. The Viterbi algorithm is complex and requires a large memory and delay. In this paper, an alternative sub‐optimal decoder based on the artificial neural network (ANN) is proposed and studied using a sliding block decoding algorithm. The ANN is trained in a supervised manner and the system parameters are optimised using computer simulations for the optimum performance. Comparative study with the Viterbi decoder is carried out. The performance of the ANN decoder is found to be comparable to the Viterbi ‘soft’ decoding with much reduced decoding length. The key advantages of the proposed ANN decoder compared with other ANN decoders are the reduced decoding and training length, adaptive decoding, no iteration required and possibility of parallel decoding. Copyright © 2012 John Wiley &amp; Sons, Ltd.

Viterbi decoding is a path maximum-likehood decoding algorithm widely used in modems and error correction devices. The Levenshtein distance has been postulated to be a suitable branch comparison metric for the Viterbi algorithm on channels not only with substitution errors, but also with insertion/deletion errors. However, to a large extent, this hypothesis has still to be investigated. Pruned convolutional codes are constructed by periodically deleting branches in a high rate convolutional code trellis diagram to create a time varying code. The application of rate compatible pruned codes to hybrid ARQ/FEC schemes is proposed here for channels with insertion, deletion and substitution errors. A new type of Viterbi algorithm based on the Levenshtein distance metric is used as the decoding algorithm. Our experiments give evidence that the Viterbi algorithm with the Levenshtein distance metric is suitable as a decoder on channels with both substitution errors and insertion/deletion errors, and furthermore that rate-compatible pruned codes can improve the performance of the decoding

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the minimized method (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 /spl mu/ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude.

For its proven efficiency, the Viterbi algorithm is widely used for decoding convolutionally encoded messages. In this work, a high performance generic soft input hard output Viterbi decoder is presented and prototyped on an FPGA board. The presented Viterbi decoder is intended to be used in a complete wireless LAN transceiver prototype. The genericity of the design facilitates not only the prototyping of Viterbi decoders with different specifications, but moreover it facilitates the exploration the performance of different implementations in order to obtain the most suitable solution for a particular communication system.

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

The Viterbi algorithm is widely applied to problems of the state estimation of a finite-state discrete-time Markov process, such as convolutional and trellis decoding. Although conventional Viterbi decoders process all states concurrently, the sequential nature of this algorithm limits the decoding throughput for a given integrated circuit technology and thereby restricts its applications. This paper presents the architecture of a single-chip Viterbi decoder combining two methods to speed-up the data rate: the "radix" trellis method and the interleaved method. The resulting architecture is very attractive for applications where high-speed decoding is essential, such as satellite digital communication systems.