A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation

In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware.

In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6 K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5 mW at 100 MHz.

In this paper, a low-power design of Viterbi decoder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and efficient reduce the average number of survivor paths. Furthermore, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit environmental requirements. The authors present a reformulation based VLSI architecture for threshold selection for adaptive Viterbi decoding in wireless applications. Through reformulation of the adaptive Viterbi algorithm, the compare operation for threshold selection in the add compare select (ACS) unit is simplified from variable based to constant based and the width of the path metric is reduced. The reformulated architecture results in a significant reduction of hardware complexity in both standard cell and look up table (LUT) technologies. The paper describes the reformulation technique, its VLSI architecture for adaptive Viterbi decoding and its implementations in both ASIC and FPGA technologies. We also demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric memory unit (PMU).

Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.

In this paper we investigate power dissipation for the Viterbi algorithm. We modified the Viterbi algorithm in a power-aware way and employed several low-power techniques to reduce its power dissipation. The first modification is re-arranging of arithmetic operations to reduce the number and complexity of computational components. Another simplification is made in the survivor memory unit by storing only one bit to identify the previous state in the survivor path, and by assigning each register to the decision vector of each clock cycle. This approach eliminates unnecessary shift operations and enables us to apply a clock-gating technique to disable all of the registers but one. The final modification stems from the property of converging all of the trace-back paths at a same state regardless of their initial state. Thus, there is no need to store a global winner path. The schemes employed in our low-power design are precomputation, clock-gating, toggle filtering, and using double edge-triggered flip-flops. The power estimation obtained through gate level simulations indicates that the proposed design reduces the power dissipation of an original Viterbi decoder design by 88%.

ABSTRACTA Viterbi algorithm (VA) is the optimal decoding strategy for the convolutional code. The Viterbi algorithm is complex and requires a large memory and delay. In this paper, an alternative sub‐optimal decoder based on the artificial neural network (ANN) is proposed and studied using a sliding block decoding algorithm. The ANN is trained in a supervised manner and the system parameters are optimised using computer simulations for the optimum performance. Comparative study with the Viterbi decoder is carried out. The performance of the ANN decoder is found to be comparable to the Viterbi ‘soft’ decoding with much reduced decoding length. The key advantages of the proposed ANN decoder compared with other ANN decoders are the reduced decoding and training length, adaptive decoding, no iteration required and possibility of parallel decoding. Copyright © 2012 John Wiley & Sons, Ltd.

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

VLSI Implementation of a Rate Decoder for Structural LDPC Channel Codes

Compared with the conventional SC-List decoder, adaptive SC-List decoder can achieve similar performance but with significantly average complexity reduce. Based on the implementation of adaptive SC-List decoder, we found a phenomenon in simulation that when the adaptive L is less than or equal to 4, there is no small probability to get the first candidate path through CRC. For the phenomenon, we proposed a repeated-part adaptive SC-List decoder, which repeat the decoding process when the value of adaptive L (searching width) is less than or equal to 4. Simulation results show that the new decoder can significantly reduce the complexity of AD-SCL algorithm with not obvious bit error rate performance improvement.

The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.

The objective of this paper is to implement SPIHT and WDR image coder. We have used here two different images Natural and Artificial. Artificial image stand for image on which enhancement techniques have been applied e.g Wallpaper whereas Natural image is an image on which no enhancement technique has been applied e.g image captured by camera directly. SPIHT stands for Set Partitioning in Hierarchical Trees (SPIHT) Coding. The SPIHT coder is a highly refined version of the EZW algorithm and is a powerful image compression algorithm that produces an embedded bit stream from which the best reconstructed images in the mean square error sense can be extracted at various bit rates. Some of the best results -- highest PSNR values for given compression ratios for a wide variety of images have been obtained with SPIHT. Hence, it has become the benchmark state-of-the-art algorithm for image compression. One of the defects of SPIHT is that it only implicitly locates the position of significant coefficients. This makes it difficult to perform operations which depend on the position of significant transform values, such as region selection on compressed data. Region selection, also known as region of interest (ROI), means a portion of a compressed image that requires increased resolution. Such compressed data operations are possible with the WDR algorithm of Tian and Wells. The term difference reduction refers to the way in which WDR encodes the locations of significant wavelet transform values. Although WDR will not produce higher PSNR values than SPIHT. With the implementation of these algorithms we have calculated the various parameters e.g. CR, PSNR, BPP & MSE to analyze PQS (picture Quality Scale). We have analyzed our results using various wavelet filters such as Biorthogonal, Coif lets, Daubechies and Symlets etc.

There is tremendous scope for improving the energy efficiency of embedded vision systems by incorporating programmable region-of-interest (ROI) readout in the image sensor design. In this work, we study how ROI programmability can be leveraged for vision applications by anticipating where the ROI will be located in future frames and switching pixels off outside of this region. We refer to this process of ROI prediction and corresponding sensor configuration as adaptive subsampling. Our adaptive subsampling algorithms comprise an object detector and an ROI predictor (Kalman filter) which operate in conjunction to optimize the energy efficiency of the vision pipeline with the end task being object tracking. To further facilitate the implementation of our adaptive algorithms in real systems, we select a candidate algorithm and map it onto an FPGA. Leveraging Xilinx Vitis AI tools, we designed and accelerated a YOLO object detector-based adaptive subsampling algorithm. In order to further improve the algorithm post-deployment, we evaluated several competing baselines on the OTB100 and LaSOT datasets. We found that coupling the ECO tracker with the Kalman filter has a competitive AUC score of 0.4568 and 0.3471 on the OTB100 and LaSOT datasets respectively. Further, the power efficiency of this algorithm is on par with, and in a couple of instances superior to, the other baselines. The ECO-based algorithm incurs a power consumption of approximately 4 W averaged across both datasets while the YOLO-based approach requires power consumption of approximately 6 W (as per our power consumption model). In terms of accuracy-latency tradeoff, the ECO-based algorithm provides near-real-time performance (19.23 FPS) while managing to attain competitive tracking precision.

Although Java has many useful programming language features for developing consumer multimedia applications, it is not widely used for multimedia application development. One of the main reasons for the lack of Java usage in consumer multimedia application development is a concern for the execution speed of Java-based applications. In this paper, we investigate the feasibility of using Java as a language for multimedia applications. As a specific multimedia application example, we have developed a Java-based MPEG-1 video decoder. We describe the design and implementation of the MPEG-1 video decoder and report our experience in optimizing the decoding performance. Based on the performance analysis results from a Java performance profiler, we have applied both general and Java-specific optimization techniques. The final implementation could decode about 28.67 frames per second on a Pentium-II 300 MHz computer for a 240/spl times/170 MPEG-1 video bitstream, a speed-up of 2.8 times over the initial implementation. Our experience strongly suggests that the pure Java-based media processing is a feasible solution.

Todays need is for increased content and bandwidth to drive communication systems, error control coding has a great demand. To maintain high reliable data and to improve the Bit Error Rate (BER), error correction technique like the Viterbi algorithm is one of the promising solutions. Though it is useful for error correction it dissipates large power. A lot many researches were carried out at architectural as well as algorithmic level to optimize the ACS (Add compare and Select) unit and Survival Memory Management in Synchronous Viterbi Decoders. But still there is a problem of power dissipation which requires more technical solutions. Due to requirements of high speed, low power, low weight and long battery life a low power Viterbi decoders has a great demand in the communication field. This paper proposed the method for survivor path storage and decoding as Minimum Transition Hybrid Register Exchange Method along with handshaking protocol as Level Encoded dual rail (LEDR) encoding to make the system asynchronous. The whole system has been designed on algorithmic level and Simulation is done on Xilinx Tool for Asynchronous Viterbi Decoder using MTHREM.