Behavioural synthesis of an adaptive Viterbi decoder

In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware.

In this paper, the design and FPGA implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the adaptive Viterbi algorithm is used. A scheme for providing a tolerance to clock-to-data skew to avoid timing violation is proposed. A process of eliminating spurious toggles, for reducing power consumption, is also developed. It is shown that the total power consumption in the implementation of the adaptive algorithm can be reduced by up to 43% compared to that in the implementation of a corresponding non-adaptive Viterbi algorithm, with a negligible increase in the hardware.

ABSTRACTA Viterbi algorithm (VA) is the optimal decoding strategy for the convolutional code. The Viterbi algorithm is complex and requires a large memory and delay. In this paper, an alternative sub‐optimal decoder based on the artificial neural network (ANN) is proposed and studied using a sliding block decoding algorithm. The ANN is trained in a supervised manner and the system parameters are optimised using computer simulations for the optimum performance. Comparative study with the Viterbi decoder is carried out. The performance of the ANN decoder is found to be comparable to the Viterbi ‘soft’ decoding with much reduced decoding length. The key advantages of the proposed ANN decoder compared with other ANN decoders are the reduced decoding and training length, adaptive decoding, no iteration required and possibility of parallel decoding. Copyright © 2012 John Wiley & Sons, Ltd.

New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit environmental requirements. The authors present a reformulation based VLSI architecture for threshold selection for adaptive Viterbi decoding in wireless applications. Through reformulation of the adaptive Viterbi algorithm, the compare operation for threshold selection in the add compare select (ACS) unit is simplified from variable based to constant based and the width of the path metric is reduced. The reformulated architecture results in a significant reduction of hardware complexity in both standard cell and look up table (LUT) technologies. The paper describes the reformulation technique, its VLSI architecture for adaptive Viterbi decoding and its implementations in both ASIC and FPGA technologies. We also demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric memory unit (PMU).

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

Power and area optimized adaptive Viterbi decoder for high speed communication applications

Design of Systems-on-Chip has become very common especially with the remarkable advances in the field of high-level system modeling. In recent years, Matlab also offers a Simulink interface for the design of hardware systems. From a high-level specification, Matlab provides self-generation of HDL codes and/or FPGA configuration codes while providing other benefits of easy simulation. In addition, a large part of the Systems-on-Chip use at least one image processing algorithm and at the same time border detection is one of the most used algorithms. This paper presents a study and a hardware implementation of various algorithms of borders detection realized under Xilinx System-Generator. The various algorithms are implemented using Xilinx FPGA device, the simulation and synthesis results are also compared. We use the Xilinx Zed-Board for physical implementations in-the-loop.

In this paper, a low-power design of Viterbi decoder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and efficient reduce the average number of survivor paths. Furthermore, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

Adaptive bounded computational and memory requirements for a Viterbi decoder can be achieved using an error trapping Viterbi decoder algorithm initially develop for hybrid automatic repeat request (ARQ) implementations. Partial path metrics and a sliding window are used to eliminate unreliable paths in the decoder trellis thus reducing the computational and memory requirements. An ARQ is issued if all paths are eliminated. The algorithm is adaptive allowing the receiver to dynamically allocate memory and processing, to improve reliability or received packets, or to reject packets with lower reliability to avoid buffer overruns. The result is the ability to trade off resources versus delay and throughput.

The HF transmission channel is characterized by severe distortions and very fast variations; in order to allow high speed data communications, very complex demodulators are required, employing both fast adaptive algorithms and sophisticated decoders. This paper reports the results of a study for the realization of 8PSK adaptive serial modem for communication in the HF frequency range. The modem operates with 2400 Baud, PSK modulation, over a 300-3400 Hz voiceband channel. Two problems have to be solved to allow efficient use of the available voiceband: channel identification, that is adaptive estimation of the channel impulse response, and optimum data decoding, this latter not being separated from some kind of adaptive equalization of the received signal. The choice for the decoding algorithm has fallen on a modified Viterbi algorithm decoder due to its superior performance with respect to more simple decoders. The decoder is preceeded by an adaptive equalizer. Both the decoder and the equalizer are driven by an adaptive estimator and the overall structure of the modem is shown.

This paper describes the hardware design of a high speed Viterbi decoder for the IEEE 802.11a Wireless Local Area Networks (WLAN) application. A fully parallel Add-Compare-Select (ACS) and trace-back architecture is presented to achieve the decoding rate up to 54Mbps. Modulation scheme and coding rate dependent quntaization accuracy for soft decision Viterbi decoding is explored and a hardware implementation scheme with run-time configurable bit-length for soft decision is then proposed to reduce the system power consumption.

A low-power and real-time hidden Markov model (HMM) accelerator is proposed for gesture user interfaces on wearable smart devices. HMM algorithm is widely used for sequence recognitions such as speech recognition and gesture recognition due to its best-in-class recognition accuracy. However, the HMM algorithm incorporates high computational complexity and requires massive memory bandwidth for sequence matches. There have been studies on hardware acceleration of the HMM algorithm to resolve these issues, but they were focused on the speech recognition and did not incorporate the motion orientation capability required for the gesture recognition case. In this paper, we propose an HMM accelerator incorporating the motion orientation block for gesture recognitions on wearable devices. Binary search is exploited in the motion orientation to avoid the division and arctangent associated with the orientation and reduce its arithmetic complexity. In addition, gesture models are clustered in the gesture database to save the memory bandwidth by reducing memory transactions. Moreover, logarithmic arithmetic is used in Viterbi decoding in the HMM for more reduction in its complexity. Thanks to these schemes, this work achieves 25.6% power reduction compared with a plain hardware implementation of the gesture recognizing HMM.

Arithmetic coding (AC) is widely used for lossless data compression, and parallelization of arithmetic coding is relatively simple because all symbols can be encoded independently. On the other hand, Parallel adaptive arithmetic coding stores the data model for each data block (the model contains the data structure used to calculate the probability distribution of the data) and these data models need to be frequently accessed and modified during encoding and decoding, so the access latency and computational complexity of the data model are important factors affecting performance. In this paper, we present a new data structure called partial prefix sum array which can quickly calculate the probability distribution of the data, so that parallel adaptive arithmetic encoding and decoding can be accelerated. Furthermore, we use a mode of coalescing access to access global memory, thereby improving the throughput of global memory. Experimental results for 6 files on NVIDIA Tesla M60 GPU show that our GPU adaptive arithmetic encoding and decoding run 1.61x- 2.75x times and 1.03x-2.22x times faster than previously presented GPU implementation, respectively.

In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.

The problem of generating symbol-by-symbol soft decision metrics (SbSSDMs) in the presence of unknown channel parameters is considered. The motivation for this work lies in its application to iterative decoding of high-performance turbo-like codes, transmitted over channels that introduce unknown parameters in addition to Gaussian noise. Traditional methods for the exact evaluation of SbSSDMs involve exponential complexity in the sequence length. A class of problems is identified for which the SbSSDMs can be exactly evaluated with only polynomial complexity with respect to the sequence length. Utilizing the close connection between symbol-by-symbol and sequence detection, it is also shown that for the aforementioned class of problems, detection of an uncoded data sequence in the presence of unknown parameters can be performed with polynomial complexity. The applicability of this technique is demonstrated by considering the problem of iterative detection of low-density parity-check codes in the presence of unknown and time-varying carrier-phase offset. Finally, based on the proposed exact schemes, an ultra-fast approximate algorithm for performing joint iterative decoding and phase estimation is derived that is well suited for hardware implementation.