FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

In this paper, the design and FPGA implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the adaptive Viterbi algorithm is used. A scheme for providing a tolerance to clock-to-data skew to avoid timing violation is proposed. A process of eliminating spurious toggles, for reducing power consumption, is also developed. It is shown that the total power consumption in the implementation of the adaptive algorithm can be reduced by up to 43% compared to that in the implementation of a corresponding non-adaptive Viterbi algorithm, with a negligible increase in the hardware.

New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit environmental requirements. The authors present a reformulation based VLSI architecture for threshold selection for adaptive Viterbi decoding in wireless applications. Through reformulation of the adaptive Viterbi algorithm, the compare operation for threshold selection in the add compare select (ACS) unit is simplified from variable based to constant based and the width of the path metric is reduced. The reformulated architecture results in a significant reduction of hardware complexity in both standard cell and look up table (LUT) technologies. The paper describes the reformulation technique, its VLSI architecture for adaptive Viterbi decoding and its implementations in both ASIC and FPGA technologies. We also demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric memory unit (PMU).

Error-correcting convolutional codes provide a proven mechanism to limit the effects of noise in digital data transmission. Although hardware implementations of decoding algorithms, such as the Viterbi algorithm, have shown good noise tolerance for error-correcting codes, these implementations require an exponential increase in very large scale integration area and power consumption to achieve increased decoding accuracy. To achieve reduced decoder power consumption, we have examined and implemented decoders based on the reduced-complexity adaptive Viterbi algorithm (AVA). Run-time dynamic reconfiguration is performed in response to varying communication channel-noise conditions to match minimized power consumption to required error-correction capabilities. Experimental calculations indicate that the use of dynamic reconfiguration leads to a 69% reduction in decoder power consumption over a nonreconfigurable field-programmable gate array implementation with no loss of decode accuracy.

In this paper, a low-power design of Viterbi decoder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and efficient reduce the average number of survivor paths. Furthermore, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

ABSTRACTA Viterbi algorithm (VA) is the optimal decoding strategy for the convolutional code. The Viterbi algorithm is complex and requires a large memory and delay. In this paper, an alternative sub‐optimal decoder based on the artificial neural network (ANN) is proposed and studied using a sliding block decoding algorithm. The ANN is trained in a supervised manner and the system parameters are optimised using computer simulations for the optimum performance. Comparative study with the Viterbi decoder is carried out. The performance of the ANN decoder is found to be comparable to the Viterbi ‘soft’ decoding with much reduced decoding length. The key advantages of the proposed ANN decoder compared with other ANN decoders are the reduced decoding and training length, adaptive decoding, no iteration required and possibility of parallel decoding. Copyright © 2012 John Wiley & Sons, Ltd.

The paper describes a novel development of the Viterbi algorithm detector that is suitable for the detection of a convolutionally coded digital signal. The technique enables a substantial reduction in equipment complexity to be achieved, relative to that of the Viterbi algorithm detector, with only a very small reduction in tolerance to noise. Results of computer-simulation tests are presented showing the performance of the system and giving also a measure of its complexity, for the particular case of a coded 8-level PSK signal. An outline is also presented of a possible implementation of the new detector for the given application.

Compared with the conventional SC-List decoder, adaptive SC-List decoder can achieve similar performance but with significantly average complexity reduce. Based on the implementation of adaptive SC-List decoder, we found a phenomenon in simulation that when the adaptive L is less than or equal to 4, there is no small probability to get the first candidate path through CRC. For the phenomenon, we proposed a repeated-part adaptive SC-List decoder, which repeat the decoding process when the value of adaptive L (searching width) is less than or equal to 4. Simulation results show that the new decoder can significantly reduce the complexity of AD-SCL algorithm with not obvious bit error rate performance improvement.

Adaptive bounded computational and memory requirements for a Viterbi decoder can be achieved using an error trapping Viterbi decoder algorithm initially develop for hybrid automatic repeat request (ARQ) implementations. Partial path metrics and a sliding window are used to eliminate unreliable paths in the decoder trellis thus reducing the computational and memory requirements. An ARQ is issued if all paths are eliminated. The algorithm is adaptive allowing the receiver to dynamically allocate memory and processing, to improve reliability or received packets, or to reject packets with lower reliability to avoid buffer overruns. The result is the ability to trade off resources versus delay and throughput.

The trellis-based decoding of Reed-Muller code (RM) has superior error performance amongst the RM decoding algorithms. However, the problem of the associated complexity limits its hardware implementation. The trellis complexity of the Reed-Muller codes, as any linear block codes, can be measured in terms of the state and branch complexities. To reduce the associated complexity of the trellis-based decoding, two major successful improvements have been introduced to the trellis structure of Reed-Muller code; sectionalization of a trellis, and parallel decomposition into sub-trellis. This work focuses on the decomposed implementation of the Reed-Muller trellis code into parallel identically sub-trellis (isomorphic) without any cross connection. We will introduce a novel complexity reduction approach to these decomposed RM code that can early terminate the decoding process of the conventional Viterbi algorithm (VA). The proposed early terminating Viterbi algorithm (ETVA) can eliminate 50% of the sub-trellises while maintaining the same error performance of the conventional VA. The gained results are of special interest for power limited space communication applications.

Communication systems performance over the Ka-band satellite channel is sensitive to the severity of weather conditions, particularly in the event of rainfall, so the use of robust channel coding with superior results is a crucial way to mitigate the effect of rainfall. As satellites are known to have power limitations, it will be efficient to use such strategies but with a decrease in complexity. RSCC Codes are standard forward error correction strategies for space communication systems that can fix errors and endure rainfall but with extra processing time and power consumption for the decoder. In this paper, we are introducing an overview of the rain fade impact throughout Ka-band satellite communication and developing a model of the rainfall fade channel. Besides, we suggest a reduced complexity Viterbi algorithm built upon a modified adaptive Viterbi algorithm. The current work achieves similar error performance as the conventional RSCC and significantly reduces computing loads and memory demands.

The combination of the channel fading compensation technique and the coded modulation technique is discussed. The system presented is considered to operate under correlated Rayleigh or Rician fading channels. The channel correlation property has been used to carry out channel fading compensation with the aid of periodically inserted pilot symbols. A multidimensional BCM (block coded modulation) scheme was used to improve the system error performances. On decoding, a corresponding trellis is used; therefore, the Viterbi algorithm and channel state information become available. The error performances of the system are investigated through computer simulations. Combined with the fading compensation, the multidimensional BCM scheme gives good error performances under various fading channels. For the Rayleigh fading channel, 7.5-dB coding gain has been achieved at a bit error rate (BER) of 10/sup -3/. For the Rician fading channel with K=10 dB, the coding gain is 3.7 dB at BER=10/sup -4/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the minimized method (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 /spl mu/ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude.

Mutithreshold decoding for convolutional codes implementing optimization methods to correct errors based on the search of global extremum of functionals in discrete spaces are considered. The implementation of divergent coding methods with triple concatenation to achieve highly efficient decoding near channel capacity is described. The possibilities of this approach while using concatenation are shown. Multialgorithmic decoding is offered. It implements the principle of divergence with simultaneous usage of two types of decoders: Viterbi algorithm and multithreshold decoding. The implementation of multialgorithmic decoding is shown to substantially decrease decoding complexity at low signal to noise ratio.

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6 K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5 mW at 100 MHz.