Performance analysis of BMC and Decision Units in the differential analog Viterbi decoder

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

Since 1967, Viterbi decoder is considered to be the maximum-likelihood decoding algorithm for convolutional codes and codes with state machine representation. Distance-preserving mapping codes designed from the mapping of convolutional codes outputs to permutation sequences make use of constructions that help choosing the best mapping and improving the performance of Viterbi decoding by improving the distances metrics in the trellis diagram of the code. Combining these new designed codes with M-FSK modulation is to combat permanent frequency disturbances in power-line communications channel. The choice of the M-FSK detector also plays a role in the improvement of the decoding process at the demodulator. Viterbi's ratio Threshold test (VRTT) is modified to avoid the erasure detection, as we are not interested in such errors in our channel and to be considered as a soft decision detection for the envelope detector.

The puncturing technique allows obtaining high-rate convolutional codes from low-rate convolutional codes used as mother codes. This technique has been successfully applied to generate good high-rate convolutional codes which are suitable for Viterbi and sequential decoding. In this paper, we investigate the puncturing technique for convolutional self-doubly orthogonal codes (CSO/sup 2/C) which are decoded using an iterative threshold-decoding algorithm. Based on an analysis of iterative threshold decoding of the rate-R=b/(b+1) punctured systematic CSO/sup 2/C, the required properties of the rate-R=1/2 systematic convolutional codes (SCCs) used as mother codes are derived. From this analysis, it is shown that there is no need for the punctured mother codes to respect all the required conditions, in order to maintain the double orthogonality at the second iteration step of the iterative threshold-decoding algorithm. The results of the search for the appropriate rate-R=1/2 SCCs used as mother codes to yield a large number of punctured codes of rates 2/3/spl les/R/spl les/6/7 are presented, and some of their error performances evaluated.

A serial concatenated convolutional and differential coding scheme is employed in a multi-user direct-sequence code-division multiple-access (DS-CDMA) system. The system consists of single-user detectors (SUDs), which are used to suppress multiple-access interference (MAI) with no requirement of other users' spreading codes, timing, or phase information. The differential code, treated as a convolutional code of code rate 1 and memory 1, does not sacrifice the coding efficiency and has the least number of states. The iterative process exchanges information between the differential decoder and the convolutional decoder. Both component decoders adopt the a posteriori probability (APP) algorithm. Numerical results in additive white Gaussian noise (AWGN) channels show that this concatenated coding scheme provides better performance and more flexibility than conventional convolutional codes in DS-CDMA systems, even in the sense of similar complexity. Further study shows that the performance of this coding scheme applied to DS-CDMA systems with SUDs improves by increasing the processing gain or the number of taps of the interference suppression filter, and degrades for higher near–far interfering power or additional near–far interfering users.

ABSTRACTA Viterbi algorithm (VA) is the optimal decoding strategy for the convolutional code. The Viterbi algorithm is complex and requires a large memory and delay. In this paper, an alternative sub‐optimal decoder based on the artificial neural network (ANN) is proposed and studied using a sliding block decoding algorithm. The ANN is trained in a supervised manner and the system parameters are optimised using computer simulations for the optimum performance. Comparative study with the Viterbi decoder is carried out. The performance of the ANN decoder is found to be comparable to the Viterbi ‘soft’ decoding with much reduced decoding length. The key advantages of the proposed ANN decoder compared with other ANN decoders are the reduced decoding and training length, adaptive decoding, no iteration required and possibility of parallel decoding. Copyright © 2012 John Wiley & Sons, Ltd.

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost is examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/s constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

In this paper, the performance comparison of serially concatenated Recursive systematic convolutional (RSC) code system with Non-systematic convolutional (NSC) code system is conduct. The two models of serially concatenated convolutional code is tested over Additive White Gaussian (AWGN) channel, Binary Phase-Shift Keying (BPSK) modulation and Viterbi decoder using MATLAB simulation. In first model of serially concatenated convolutional code uses Recursive systematic convolutional (RSC) as outer and inner encoder. In second model of serially concatenated convolutional code uses Non-systematic convolutional (NSC) as outer and inner encoder. The outer and inner encoders are concatenated with the help of interleaver. For decoding a non-iterative Viterbi decoding scheme is performed with two Viterbi decoder are concatenated by de-interleaver. The MATLAB simulation results shows that the performance of RSC-RSC concatenated code gives the better bit error rate (BER) than the NSC-NSC concatenated code.

Consideration is given to the bit error probability performance of rate 1/2 convolutional codes in conjunction with quaternary phase shift keying (QPSK) modulation and maximum-likelihood Viterbi decoding on fully interleaved Rician fading channels. Applying the generating function union bounding approach, an asymptotically tight analytic upper bound on the bit error probability performance is developed under the assumption of using the Viterbi decoder with perfect fading amplitude measurement. Bit error probability performance of constraint length K=3-7 codes with QPSK is numerically evaluated using the developed bound. Tightness of the bound is examined by means of computer simulation. The influence of perfect amplitude measurement on the performance of the Viterbi decoder is observed. A performance comparison with rate 1/2 codes with binary phase shift keying (BPSK) is provided. >

In this paper, two novel interleaving schemes suitable for a convolutional code are given as the block interleaving scheme and bit interleaving scheme. Based on convolutional coding with Viterbi decoding, the anti-interference performance of the (2,1,3) convolutional code using these two schemes in a mobile image communication system is studied and compared with the performance using traditional periodic interleaving scheme. The simulation results show that periodic interleaving scheme is not suitable for a convolutional code. The reliability of an image transmission system in a fast fading mobile channel can be improved greatly by adopting the (2,1,3) convolutional code combined with block interleaving scheme or bit interleaving scheme as the anti-interference measure.

This paper addresses the implementation and performance of hybrid-ARQ error control on a coherent slowly fading Ricean channel. Using a convolutional code with soft-decision Viterbi decoding for error correction, there are two methods for realizing the simultaneous error detection capability which characterizes hybrid-ARQ error control: (1) a two code approach which pre-encodes the information based on a high rate CRC code and performs error detection on the output of the Viterbi decoder, (2) a single code approach which modifies the Viterbi decoder to reject packets with low reliability during the Viterbi decoding process. The resulting analysis shows that the two code method is more robust than single code method with the most significant performance advantages realized for Rayleigh fading. The two code approach provides acceptable error rate performance and offers a throughput characteristic which is not as sensitive to changes in the average SNR as the single code approach. Since the implementational complexity of the two methods is comparable, the two code method is the preferred implementation for hybrid-ARQ on flat fading channels.

A Viterbi decoding algorithm with a scarce-state transition-type circuit configuration, namely the probability selecting states (PSS) mode decoder, is presented. The algorithm has reduced complexity compared to a conventional Viterbi decoder. It is shown that this method has three advantages over the general Viterbi algorithm: it is suitable to the quick look-in code, it applies the optimum decoding in a PSS-type decoder, and it makes full use of the likelihood concentration property. The bit-error-rate (BER) performance of a r=1/2, k=7 (147,135) code and PSS-type Viterbi decoder approximates the optimum performance of the standard Viterbi decoder and reduces the hardware of the conventional Viterbi decoder to about half.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Convolutional codes are channel codes, which are extensively used in communication systems like GSM (global system for mobile communications) and Interim standard IS-95.We introduce a strategy to present convolutional codes to students learning wireless communication systems, digital communication or similar courses, without using mathematical structures.In this paper, we will discuss our method to implement convolutional encoding and Viterbi decoding to determine the bit error rate.We have compared its performance under different conditions.To exemplify and illuminate our approach, we have selected a communication channel with rate 1/3 convolutional code.Constrain length is three for both Viterbi hard decision decoding method and Viterbi soft decision decoding method.Results suggest that soft decision decoding has at least 3.24 dB improvements in SNR compared to hard decision decoding for same bit error rate.Also by using soft decision Viterbi decoding on AWGN channel, we have examined various convolutional codes for four different constrain lengths and rates.We find that the first code with rate 1/3 code and constrain length 3 has better bit error rate performance with respect to other coding methods.This means, it gives a lower bit error rate for the same value of signal to noise ratio used in other coding schemes.Thus, to achieve the same bit error rate the first code will require a lower SNR.A lower SNR means a lower transmitter power.However, if we use this code the bandwidth requirement is three times larger compared with an un-coded transmission.For the second coding scheme we have an increase in bandwidth by a factor of 2 and for the third and fourth coding scheme the increase factor is 1.5.We believe this approach and its corresponding results will expose students to conceptual and technical aspects of signal encoding and its analysis.