Analysis of non-blocking ATM switches with multiple input queues

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.

An analytical model for the performance analysis of a novel input access scheme for an ATM switch is developed and presented in this paper. The interconnection network of the ATM switch is internally nonblocking and is provided with N input queues per each input port for a switch of size N × N. That is, each input port maintains a separate queue for each output port so as to reduce the head-of-line (HOL) blocking of conventional input queuing switches. Each input is allowed to send just one cell per slot time, and each output port is allowed to accept just one cell per slot time. Under saturated conditions the switch was analyzed and a closed-form solution for the maximum throughput is derived. Using a tagged input queue approach, an analytical model for evaluating the switch performance under an i.i.d. Bernoulli traffic for different offered traffic loads is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.

In this letter, we analyze the performance of multiple input-queued asynchronous transfer mode (ATM) switches that use parallel iterative matching (PIM) for scheduling the transmission of head-of-line cells in the input queues. A queueing model of the switch is developed under independently, identically distributed, two-state Markov modulated Bernoulli processes bursty traffic. The underlying Markov chain of the queueing model is a quasi-birth-death (QBD) chain. The QBD chain is solved using an iterative computing method. Interesting performance metrics of the ATM switch such as the throughput, the mean cell delay, and the cell loss probability can be derived from the model. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is briefly discussed.

The multiple input-queued (MIQ) switch is the switch which manages multiple (m) queues in each input port, each of which is dedicated to a group of output ports. Since each input port can switch up to m cells in a time slot, one from each queue, it hardly suffers from the head-of-line (HOL) blocking which is known to be the decisive factor limiting the throughput of the single input-queued (SIQ) switch. As a result, the MIQ switch guarantees enhanced performance characteristics as the number of queues m in an input increases. However, the service of multiple cells from an input could cause internal speedup or expansion of the switch fabric, diluting the merit of high-speed operation in the conventional SIQ scheme. The restricted rule is contrived to circumvent this side effect by regulating the number of cells switched from an input port. We analyze the performance of the MIQ switch employing the restricted rule. For the switch using the restricted rule, the closed formulas for the throughput bound, the mean cell delay and average queue length, and the cell loss bound of the switch are derived as functions of m, by generalizing the analysis for the SIQ switch by J.Y. Hui and E. Arthurs (see IEEE J. Select. Areas Commun., vol.SAC-5, p.1262-73, 1987).

Output Queuing (OQ) and Input Queuing (IQ) are the two basic queuing strategies implemented in routers. IQ has been identified as the simplest and the most scalable. However, the IQ only achieves 58.6% throughput due to the Head Of Line (HOL) blocking effect. The Virtual Output Queuing (VOQ) strategy is a proffered solution to the HOL blocking. It has been shown that VOQ can achieve a 100% throughput with an effective scheduling algorithm. This paper proposes a Multi stage Queuing and Scheduling architecture in which VOQ is implemented at the input and OQ at the output. The scheduling algorithm for the VOQ presented in this paper is an Iterative Probabilistic Scheduling.

This letter derives the saturated throughput for a buffered crossbar switch with multiple queues at each input port under uniform burst traffic. The accuracy of the theoretic analysis is also investigated by extensive simulation.

ATM switches have been proposed as the switching fabric cores of many high-performance IP switches. In this paper, we present an efficient algorithm called IP-PIM for scheduling variable-length IP packets on these switches and compare its performance with the original parallel iterative matching (PIM) ATM cell scheduling algorithm. The mean IP packet delays using both the PIM and the IP-PIM scheduling algorithms are analyzed using queueing analysis and extensive simulations. Our results demonstrate that the packet level scheduling such as the IP-PIM could be a potential way to significantly improve the performance of PIM switches, especially in the context of IP networks.

Performance analysis of statistical multiplexing of heterogeneous discrete-time Markovian arrival processes in an ATM network

Performance analysis of packet switches with input and output buffers

The authors study the performance of a non-blocking space-division packet switch, which experiences nonuniform traffic intensities that also change as a function of time. A finite-state Markov chain is used as an underlying process to govern the time variation of traffic for the entire switch. The packet arrivals at each input form an independent Bernoulli process modulated by the underlying Markov chain. Also, the output address of each packet is independently and randomly assigned with probability distributions, which are gain modulated by the Markov chain. Provided that the traffic at each output is not dominated by individual inputs, it is shown that the service time of each input queue for sufficiently large switches can be characterized by an independent Markov-modulated phase-type process. A matrix geometric solution for the resultant quasi-birth-death-type queuing process is presented. The maximum throughput is obtained at the system saturation. The performance of the switch is numerically examined under various traffic conditions. A contention priority scheme is also proposed to improve the switch performance. >

An N*N nonblocking packet switch with input queues and two priority classes that can be used to support traffic with different requirements is described. The switch operation is slotted and, at each time slot, fixed-size packets arrive at the inputs with distinct Bernoulli distributions for both the high- and low-priority classes. Two policies are discussed. In the first policy, packets of both priority classes are queued when waiting for service. In the second policy, only low-priority packets are queued, and high-priority packets not delivered at the first attempt are dropped from the system. Under both policies, high-priority packets prevail over low-priority packets at the inputs as well as the outputs. An approximate analysis that is based on independence assumptions and uses an equivalent queueing system to estimate the service capability seen be each input is presented. Using this approach, an expression for the input queue length distribution is obtained. The maximum system throughput is derived and shown to exceed that of a single priority switch. Numerical results are compared to simulations and are found to agree.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed packet switches become increasingly important to embedded systems because they provide multiple parallel data paths necessary in emerging systems such as embedded multiprocessors, multiprotocol communication processors, and so on. The most promising architecture for embedded switches is the one that uses multiple input queues, due to its low-cost integration in conventional embedded systems, which include memory management subsystems. Such switches require high-speed schedulers, in order to resolve conflicts among packet destinations and to achieve low latency, high bandwidth communication, while providing fairness guarantees. In general, these schedulers are categorized as centralized or distributed, depending on their operation. In this paper, we evaluate hardware and software implementations of two schedulers: 2-dimensional round-robin and FIRM, which are centralized and distributed, respectively. The evaluation is performed for embedded system implementation, on a system that includes an FPGA and an embedded processor on-chip. The performance results show that, in contrast to expectations, centralized schedulers provide better performance than distributed ones in hardware implementations. In software implementations for embedded processors, surprisingly, distributed schedulers achieve better performance, due to better management of the processor's limited resources and simpler code; our experiments have shown that compilers for embedded systems are quite limited and require significant improvement. Finally, we evaluate the scalability of the schedulers, in terms of throughput, circuit complexity, and power consumption, based on implementation technology, considering the dramatic improvements expected in the availability of high-speed programmable logic and embedded processors on the same chip.

Port partitioning and dynamic queueing for IP forwarding

ATM communication systems have introduced a number of new dimensioning problems, one being the evaluation of the loss probability for a shared buffer memory within a switch matrix. This is a problem of growing interest since shared buffer memory switches offer the best cell loss probability versus total buffer space provided, and thus are often the design of choice. ATM switches operate in a time slotted fashion: at the end of each slot, N cells will have been transmitted if all N servers have cells for transmission. If a server has no cell to transmit, it will produce an empty slot. Iliadis (1991) has presented a method for solving such a system based on the introduction of an N dimensional Markov chain. Schormans et al. (see Electronics Letters, vol.30, no.1, 1994) have presented a simplified algorithm for a fairly general arrival process. This paper considers certain problems in (shared) buffer dimensioning: calculation of the cell loss probability (CLP) for a 2/spl times/2 switching element, given any i/p loading; the effect, on such a shared buffer switching element, of allowing the applied traffic to approach the limit, i.e. during each time slot every input line will contain a new cell; and the relationship between the cell loss probability and the model of the routing strategy.

Virtual Output Queuing (VOQ) is widely used by input-queued (IQ) packet switches to eliminate the head-of-line (HoL) blocking problem. A lot of research has been devoted to design iterative arbitration algorithms to maximize the throughput of this architecture. Nevertheless, these approaches require either a high computation complexity or large contention resolution times for high-speed switches. We investigate in this paper the performance of various such algorithms and based on the analysis of pointer desynchronization effect, we propose a new algorithm approximating maximum size matching (MSM) called Selective Request Round Robin (SRRR) which performs extremely well under various traffic models and is easy to implement in hardware.