Analysis of nonblocking ATM switches with multiple input queues

In this letter, we analyze the performance of multiple input-queued asynchronous transfer mode (ATM) switches that use parallel iterative matching (PIM) for scheduling the transmission of head-of-line cells in the input queues. A queueing model of the switch is developed under independently, identically distributed, two-state Markov modulated Bernoulli processes bursty traffic. The underlying Markov chain of the queueing model is a quasi-birth-death (QBD) chain. The QBD chain is solved using an iterative computing method. Interesting performance metrics of the ATM switch such as the throughput, the mean cell delay, and the cell loss probability can be derived from the model. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is briefly discussed.

The performance of a non-blocking ATM switch in which each input port maintains a separate queue for each output port to overcome the head-of-line (HOL) blocking of conventional FIFO input queuing switches is presented. Parallel iterative matching (PIM) is used as the scheduling algorithm for selecting the HOL cells to be transmitted in each time slot. After deriving a closed-form solution for the maximum throughput of the switch under saturated conditions, an analytical model for evaluating the switch performance under i.i.d Bernoulli traffic is developed using the tagged input queue approach. Performance measures including throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.

An analytical model for the performance analysis of a novel input access scheme for an ATM switch is developed and presented in this paper. The interconnection network of the ATM switch is internally nonblocking and is provided with N input queues per each input port for a switch of size N × N. That is, each input port maintains a separate queue for each output port so as to reduce the head-of-line (HOL) blocking of conventional input queuing switches. Each input is allowed to send just one cell per slot time, and each output port is allowed to accept just one cell per slot time. Under saturated conditions the switch was analyzed and a closed-form solution for the maximum throughput is derived. Using a tagged input queue approach, an analytical model for evaluating the switch performance under an i.i.d. Bernoulli traffic for different offered traffic loads is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.

An efficient adaptive bus arbitration scheme for scalable shared-medium ATM switch

A terabit/second hierarchically multiplexing photonic asynchronous transfer mode (ATM) switch network architecture, called Terahipas, is proposed. It combines the advantages of photonics (a large bandwidth for transport of cells) and electronics (advanced logical functions for controlling, processing, and routing). It uses a hierarchical photonic multiplexing structure in which several tens of channels with a relatively low bit rate, say 2.4 Gb/s, are first time-multiplexed on an optical highway by shrinking the interval between optical pulses, then a number of optical highways are wavelength-multiplexed (or space-division multiplexed). As a result, the switch capacity can be expanded from the order of 100 Gb/s to the order of 10 Tb/s in a modular fashion. A new implementation scheme for cell buffering is used for eliminating the bottleneck when receiving and storing concurrent optical cells at bit rates as high as 100 Gb/s. This new architecture can serve as the basis of a modular, expandable, high-performance ATM switching system for future broad band integrated service digital networks (B-ISDN's). >

Many 'output scheduling' algorithms have been proposed for improving the performance of input-queued asynchronous transfer mode (ATM) switches, whereby cells from different random-access input queues destined for the same output can be scheduled for non-conflicting transmissions. An optimal output scheduling algorithm, with full coordination of transmission to all outputs, can approach the performance of output queueing. Because of the complexity of such an optimal scheduler, the output schedulers proposed in the literature are without such coordination. We propose a simple way to incorporate such a full coordination in output scheduling with very simple hardware. The throughput of the input queuing switch thus approaches that of the output queueing switch, without speed-up, input/ouput grouping or complicated hardware. To make the output scheduling algorithm fast enough, we incorporate parallelism and pipelining. We perform a detailed simulation study of the performance of the input queueing switch with the proposed scheduling algorithm.

Since the asynchronous transfer mode (ATM) has been strongly promoted as the transport structure for broadband integrated services digital networks, a variety of ATM switching architectures have been proposed. The knockout switch, which is one of the well known ATM switches, has a single-stage architecture and adopts an output buffering method. It has excellent traffic performance (cell loss probability, maximum throughput and delay, etc.), but needs many switch elements and buffers. The authors propose an ATM switch, called a knockout switch with input buffers. The proposed switch has almost the same traffic performance as the existing knockout switch but needs fewer switch elements and buffers than the existing knockout switch. The authors analyse the traffic performance and complexity (i.e. the number of switch elements and buffers required) of the proposed architecture by discrete-time Markov chain models and compare them with those of the existing knockout switch. It is found that the proposed architecture could reduce the need for over 40% of the switch elements and over 30% of the buffers while satisfying the given loss requirements.

A possible network architecture for a microcellular mobile telecommunication system based on packet transmission and ATM (Asynchronous Transfer Mode) switching is proposed. A full integration and internetworking with Broadband Integrated Services Digital Network are assumed. The performance of a generic nonblocking ATM switch under input traffic patterns that consider the effect of handovers is evaluated. Special attention is paid to the preservation of packet sequence integrity on a virtual channel. The generic ATM switch architecture has been analyzed under simplified network architecture assumptions by means of computer simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

General models for a class of nonblocking architectures of asynchronous transfer mode (ATM) switches are described. Hardware aspects are discussed to show the implementation feasibility of the proposed switch architectures by means of the current technology. Performance issues are studied to point out the traffic bottlenecks of the different structures. It is shown that the classification of queueing is the main concept that enables the classification of nonblocking ATM switches. Three main packet queueing strategies can be adopted in the switching fabric: input queueing, shared queueing, and output queueing. Switch architectures adopting only one of these strategies are described. The ways in which two strategies can be jointly adopted in a switching fabric to result in the mixed queueing strategies input-output queueing, input-shared queueing, and shared-output queueing are also discussed. >

This paper presents the architecture of a very high performance 4-input, 4-output asynchronous transfer mode (ATM) switch that has been designed as part of the ARPA-sponsored Thunder and Lightning project at the University of California, Santa Barbara. This research project is focused on the design and prototype demonstration of ATM links and switches operating at or above 40 gigabits per second per TDM link, with potential scalability to 100 Gbps. Such aggressive link rates place severe requirements on switch architecture, particularly the buffering scheme. In this paper we present the ATM switch structure and justify the main design choices.

The asynchronous transfer mode (ATM) has become the subject of intense interest across all segments of the telecommunications and computer industry. State-of-the-art multiplexing and switching technologies form the basis of ATM's ability to deliver different types of information (e.g., voice, data, audio, video and graphics) at gigabit speeds. ATM networks rely heavily on the efficiency and speed of their switching fabrics. In the last few years, heavy research has been conducted in the design of new ATM switching fabrics. We examine the B-tree fault-tolerant ATM switch, acknowledged to be one of the most efficient ATM switch. We show several of its shortcomings, one of which is that it does not resolve internal conflicts of data packets. We (1) extensively study the B-tree switch (2) analyze the different buffering methods that would be suitable for our design, (3) analyze the different traffic models to reflect real-time traffic, (4) exploit the information from above to design a more fault-tolerant switch, and (5) conduct extensive simulation to prove the efficacy of our design.

In interconnections between bookshelf-assembled asynchronous transfer mode (ATM) switch boards, a large number of micro-optical signal beams can be optically interconnected by a beam direction compensating system using a vertical cavity surface emitting laser, an x-y beam positioning sensor and a beam deflector made of an adjustable liquid prism. This beam direction compensating system can suppress the decrease in coupling efficiency between transmitters and receivers to no more than 15%, even if boards are inserted and extracted repeatedly, and are shocked repeatedly at a high intensity of 100 G. The compensation is very fast (20 ms). Furthermore, various optical interconnections necessary for ATM switching networks can be achieved by beam deflectors of a liquid crystal microprism array. In this preliminary study, we fabricate no more than eight-channel optical interconnections. However, since one surface emitting laser diode can have many channels in a small area (64 channels per 4 mm/sup 2/) and the aperture of this adjustable liquid prism is wide (28 mm in diameter) and uniform, a huge number of optical interconnection channels is possible using this system.

Switch design for ATM (Asynchronous Transfer Mode) networks needs to take a fresh approach in order to support ABR (Available Bit Rate) services efficiently. In particular, ATM switches designed for data communications should implement flow control functions to prevent data loss while minimizing required memory. These new requirements make the design of ATM switches fundamentally different from that of traditional switch design.

The authors examine a growable architecture for broadband packet (asynchronous transfer mode) switching, consisting of a memoryless, self-routing interconnect fabric and modest-size packet switch modules, proposed by K.U. Eng et al. (1989). They focus on the cell loss probability, because the architecture attains the best possible delay-throughput performance if the packet switch modules use output queueing. They compute an upper bound on the cell loss probability for arbitrary patterns of independent cell arrivals, possibly including isochronous circuit connections, and show that both sources of cell loss can be made negligibly small. For example, to guarantee a cell loss probability of less than 10/sup -9/, this growable architecture requires packet switch modules of dimension 47*16, 45*16, 42*16, and 39*16 for 100%, 90%, 80%, and 70% traffic loads, respectively. The analytic techniques used to bound the cell loss probabilities are applicable to other output queueing architectures. >

An ultra-high-speed asynchronous transfer mode (ATM) switching module having a highway throughput of 9.6 Gb/s using a HEMT process switch IC and a ceramic multichip substrate was developed. The switch IC operates at 1.2 Gb/s. This module provides a 4*4 switch, corresponding to a switching capacity of 256 channels at 156 Mb/s. High-speed switching is essential for constructing a large switching system with small volume and low power consumption. A simulation of both cell buffer operation and line characteristic is presented. The experimental results are shown. >