Performance analysis of the knockout switch with input buffers

A possible network architecture for a microcellular mobile telecommunication system based on packet transmission and ATM (Asynchronous Transfer Mode) switching is proposed. A full integration and internetworking with Broadband Integrated Services Digital Network are assumed. The performance of a generic nonblocking ATM switch under input traffic patterns that consider the effect of handovers is evaluated. Special attention is paid to the preservation of packet sequence integrity on a virtual channel. The generic ATM switch architecture has been analyzed under simplified network architecture assumptions by means of computer simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.

Asynchronous transfer mode (ATM) switching is studied widely as the switching method in the broadband ISDN and numerous switching methods have been proposed. In most of those methods, the deterioration of the throughput due to the internal collision of the cells is prevented in the switching network by a complex control protocol or by increasing the internal speed. In the highspeed broadband switching system such as ATM, however, it is desirable for the system that the structure and the control be simple, the internal speed not be increased, and the highly efficient switching network be realized with a nonblocking property. This paper attempts to satisfy the forementioned requirements and proposes the route‐associated buffer system in which the buffers are provided corresponding to the input and the output route, while improving the efficiency of the use of the buffers. The network configuration and the traffic control process are presented. In the traffic analysis, the poling model is defined, where the number of cells to be taken out from the individual buffer is adjusted according to the number of waiting cells. The traffic processing performance of the switching network is analyzed using the approximate method of analysis for the cyclic multiple queues. The usefulness of the method is shown by numerical analysis and simulation.

A terabit/second hierarchically multiplexing photonic asynchronous transfer mode (ATM) switch network architecture, called Terahipas, is proposed. It combines the advantages of photonics (a large bandwidth for transport of cells) and electronics (advanced logical functions for controlling, processing, and routing). It uses a hierarchical photonic multiplexing structure in which several tens of channels with a relatively low bit rate, say 2.4 Gb/s, are first time-multiplexed on an optical highway by shrinking the interval between optical pulses, then a number of optical highways are wavelength-multiplexed (or space-division multiplexed). As a result, the switch capacity can be expanded from the order of 100 Gb/s to the order of 10 Tb/s in a modular fashion. A new implementation scheme for cell buffering is used for eliminating the bottleneck when receiving and storing concurrent optical cells at bit rates as high as 100 Gb/s. This new architecture can serve as the basis of a modular, expandable, high-performance ATM switching system for future broad band integrated service digital networks (B-ISDN's). >

A prototype first in first out (FIFO) input buffer asynchronous transfer mode (ATM) switch (element) is known as the architecture in which the transfer capacity is considerably limited and needs to be improved. The parallel readout structure, and three control rules for cyclic read-out (CRO) cell selection, parallel readout random (PROR) cell selection, and parallel readout maximum (PROM) queue selection for the structure are presented as novel switch architectures. The performance of the above switches are evaluated by simulation, and the results show that the parallel readout structure can give a drastic reduction of the buffer size. For the PROR and PROM switches, a large total hardware reduction can be achieved although a small hardware increment is necessary for parallel structure. The simulation results simultaneously show that the input buffer switches have a lower loss performance than that of the output buffer, keeping the delay almost equivalent to that of the output type buffer.

The asynchronous transfer mode (ATM) has become the subject of intense interest across all segments of the telecommunications and computer industry. State-of-the-art multiplexing and switching technologies form the basis of ATM's ability to deliver different types of information (e.g., voice, data, audio, video and graphics) at gigabit speeds. ATM networks rely heavily on the efficiency and speed of their switching fabrics. In the last few years, heavy research has been conducted in the design of new ATM switching fabrics. We examine the B-tree fault-tolerant ATM switch, acknowledged to be one of the most efficient ATM switch. We show several of its shortcomings, one of which is that it does not resolve internal conflicts of data packets. We (1) extensively study the B-tree switch (2) analyze the different buffering methods that would be suitable for our design, (3) analyze the different traffic models to reflect real-time traffic, (4) exploit the information from above to design a more fault-tolerant switch, and (5) conduct extensive simulation to prove the efficacy of our design.

In this letter, we analyze the performance of multiple input-queued asynchronous transfer mode (ATM) switches that use parallel iterative matching (PIM) for scheduling the transmission of head-of-line cells in the input queues. A queueing model of the switch is developed under independently, identically distributed, two-state Markov modulated Bernoulli processes bursty traffic. The underlying Markov chain of the queueing model is a quasi-birth-death (QBD) chain. The QBD chain is solved using an iterative computing method. Interesting performance metrics of the ATM switch such as the throughput, the mean cell delay, and the cell loss probability can be derived from the model. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is briefly discussed.

An efficient adaptive bus arbitration scheme for scalable shared-medium ATM switch

Broadband networking has evolved dramatically in the past few years. Especially the asynchronous transfer mode (ATM) has attracted attention in the area of high-speed communication, promising the integration of almost all communication profiles such as voice, video and computer-based multimedia communication. As ATM builds the transport technology of broadband integrated services digital network (B-ISDN), it is to be considered as the key technology of the data-highway initiatives aimed by the majority of industrial countries. However, the topic of network security plays an important role in any publicly accessible telecommunication infrastructure. Unfortunately, the progresses made in providing for adequate network security still lag behind the evolution of B-ISDN.In this paper we give an interim report on a project aiming to information privacy in B-ISDN infrastructures. Several approaches to B-ISDN security with emphasis on confidential user-to-user communication are discussed. We compare the different approaches to ATM encryption and propose the application of a method known as ATM cell stream interception. Therefore, we apply an encryption module to an ATM network interface card (NIC) using standardized interfaces and, thus, propose an architecture that is almost independent of the hardware.KeywordsB-ISDN securityATM securityATM cell stream encryption

This paper presents the architecture of a very high performance 4-input, 4-output asynchronous transfer mode (ATM) switch that has been designed as part of the ARPA-sponsored Thunder and Lightning project at the University of California, Santa Barbara. This research project is focused on the design and prototype demonstration of ATM links and switches operating at or above 40 gigabits per second per TDM link, with potential scalability to 100 Gbps. Such aggressive link rates place severe requirements on switch architecture, particularly the buffering scheme. In this paper we present the ATM switch structure and justify the main design choices.

Broadband Integrated Services Digital Network (BISDN) is conceived as a universal digital network providing both integrated switching and services. Typical services include data, voice, video, high-resolution image, etc. [Spea 87]. Encouraged by developments of fast packet switches [Turn 85] and ATD experiments in France [Deva 88], a packet-oriented virtual circuit transfer mode, called ATM (Asynchronous Transfer Mode), has been adopted as the universal transport vehicle of BISDN services [Minz 89]. Data from various sources are segmented into fixed-size ATM cells and statistically multiplexed to high-speed transmission lines and switches. An ATM cells consists of a 5-octet header and a 48-octet payload fields. Unlike the conventional STM (Synchronous Transfer Mode) technique which switches data according to positions in recurrent structure (frame), ATM cells are switched by labels containing routing information in the headers. Label-based switching is believed to be flexible in integrating diverse traffic types, envisioned for BISDN environments.

High speed Asynchronous Transfer Mode (ATM) wireless networks are assuming a growing interest in the personal communication area [1–6]. This paper describes the design of a wireless ATM system, which is being implemented in the ’’MEDIAN‘‘ project belonging to the European Community (EC) Advance Communications Technologies and Services (ACTS) programme. The Medium Access Control (MAC) aims at providing a simple and efficient transport for ATM cells from a Base Station (BS), interfaced with the ATM Broadband Integrated Service Digital Network (B-ISDN), to ATM Portable Stations (PSs) and vice versa. A Time Division Duplex (TDD) scheme is adopted in which uplink and downlink frame durations can be varied frame-by-frame, in order to fit the present uplink/downlink traffic mix. Moreover, in the uplink, a contention-free based technique is considered in which the slots are assigned to the calls depending on the present load of the PS uplink buffers. The proposed interworking with the ATM network is based on the concept of intercepting the ATM Signalling and Management Cells at the BS, in order to deduce from the ATM Q.2931 messages information relevant to the registration, the call set-up and the MAC procedures.

Switch design for ATM (Asynchronous Transfer Mode) networks needs to take a fresh approach in order to support ABR (Available Bit Rate) services efficiently. In particular, ATM switches designed for data communications should implement flow control functions to prevent data loss while minimizing required memory. These new requirements make the design of ATM switches fundamentally different from that of traditional switch design.

In interconnections between bookshelf-assembled asynchronous transfer mode (ATM) switch boards, a large number of micro-optical signal beams can be optically interconnected by a beam direction compensating system using a vertical cavity surface emitting laser, an x-y beam positioning sensor and a beam deflector made of an adjustable liquid prism. This beam direction compensating system can suppress the decrease in coupling efficiency between transmitters and receivers to no more than 15%, even if boards are inserted and extracted repeatedly, and are shocked repeatedly at a high intensity of 100 G. The compensation is very fast (20 ms). Furthermore, various optical interconnections necessary for ATM switching networks can be achieved by beam deflectors of a liquid crystal microprism array. In this preliminary study, we fabricate no more than eight-channel optical interconnections. However, since one surface emitting laser diode can have many channels in a small area (64 channels per 4 mm/sup 2/) and the aperture of this adjustable liquid prism is wide (28 mm in diameter) and uniform, a huge number of optical interconnection channels is possible using this system.

General models for a class of nonblocking architectures of asynchronous transfer mode (ATM) switches are described. Hardware aspects are discussed to show the implementation feasibility of the proposed switch architectures by means of the current technology. Performance issues are studied to point out the traffic bottlenecks of the different structures. It is shown that the classification of queueing is the main concept that enables the classification of nonblocking ATM switches. Three main packet queueing strategies can be adopted in the switching fabric: input queueing, shared queueing, and output queueing. Switch architectures adopting only one of these strategies are described. The ways in which two strategies can be jointly adopted in a switching fabric to result in the mixed queueing strategies input-output queueing, input-shared queueing, and shared-output queueing are also discussed. >