Performance analysis of a fault-tolerant B-tree ATM switch

This paper considers a multistage interconnection network based on the Indirect Star Graph topology as a candidate for an ATM (Asynchronous Transfer Mode) switch fabric. We consider both buffered and unbuffered versions of the indirect star. The performance of three existing routing algorithms is studied, and it is found that the packet acceptance probability offered by these algorithms is unsatisfactory. We propose two solutions to alleviate the problem: a modification of the indirect star topology, which we call Star Net; and an adaptive routing algorithm based on the concept of packet priorities. We study the performance of the proposed performance enhancement schemes through simulation. >

A large-scale asynchronous transfer mode (ATM) switch fabric that can be constructed with currently feasible technology is proposed. Based on analysis of the technology, it is found that module interconnection becomes the bottleneck for a large fast packet switch. Fault tolerance for the switch is achieved by dynamic reconfiguration of the module interconnection network. The design improves system reliability with relatively low hardware overhead. An abstract model of the replacement problem for the design is presented, and the problem is transformed into a well-known assignment problem. The maximum fault tolerance is found, and a fast replacement algorithm is given. The reconfiguration capability can also be used to ameliorate imbalanced traffic flows. The authors formulate this traffic flow assignment problem for the switch fabric and show that the problem is NP-hard. A simple heuristic algorithm is proposed, and an example is given. >

This paper considers the influence of switch fabric design on the performance of resource allocation and connection admission algorithms for asynchronous transfer mode (ATM) networks. In particular, the goal of predictable and guaranteed quality of service (QoS) can be achieved within an ATM network by considering the above factors in the design of the ATM switch fabric. The paper focuses on the identification of the functional requirements of the switch fabric at the ATM layer, and develops an improved architecture which considers QoS at the switch fabric, along with an interface to the resource management. The resultant switch results in ATM networks which have reliable and predictable parameters and which have reduced complexity in connection admission control.

A possible network architecture for a microcellular mobile telecommunication system based on packet transmission and ATM (Asynchronous Transfer Mode) switching is proposed. A full integration and internetworking with Broadband Integrated Services Digital Network are assumed. The performance of a generic nonblocking ATM switch under input traffic patterns that consider the effect of handovers is evaluated. Special attention is paid to the preservation of packet sequence integrity on a virtual channel. The generic ATM switch architecture has been analyzed under simplified network architecture assumptions by means of computer simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The use of two resource-sharing techniques for congestion control in a backbone asynchronous transfer mode (ATM) network consisting of ATM cross-connects interconnected with high-speed optical links such as 2.4-Gb/s OC-48c fibers is studied. Memory sharing allows an optimal shared use of buffer space in an ATM switch fabric. Channel (or line) sharing, on the other hand, takes advantage of spare line capacity in the system to permit temporary increases in the output rates of the congested output ports. Fundamental bounds on delay-throughput performance and buffer requirements for specific cell loss rates are presented, and two practical application scenarios, representing line protection arrangements with and without service access capabilities, are introduced. >

A terabit/second hierarchically multiplexing photonic asynchronous transfer mode (ATM) switch network architecture, called Terahipas, is proposed. It combines the advantages of photonics (a large bandwidth for transport of cells) and electronics (advanced logical functions for controlling, processing, and routing). It uses a hierarchical photonic multiplexing structure in which several tens of channels with a relatively low bit rate, say 2.4 Gb/s, are first time-multiplexed on an optical highway by shrinking the interval between optical pulses, then a number of optical highways are wavelength-multiplexed (or space-division multiplexed). As a result, the switch capacity can be expanded from the order of 100 Gb/s to the order of 10 Tb/s in a modular fashion. A new implementation scheme for cell buffering is used for eliminating the bottleneck when receiving and storing concurrent optical cells at bit rates as high as 100 Gb/s. This new architecture can serve as the basis of a modular, expandable, high-performance ATM switching system for future broad band integrated service digital networks (B-ISDN's). >

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.

Switch design for ATM (Asynchronous Transfer Mode) networks needs to take a fresh approach in order to support ABR (Available Bit Rate) services efficiently. In particular, ATM switches designed for data communications should implement flow control functions to prevent data loss while minimizing required memory. These new requirements make the design of ATM switches fundamentally different from that of traditional switch design.

This paper presents the architecture of a very high performance 4-input, 4-output asynchronous transfer mode (ATM) switch that has been designed as part of the ARPA-sponsored Thunder and Lightning project at the University of California, Santa Barbara. This research project is focused on the design and prototype demonstration of ATM links and switches operating at or above 40 gigabits per second per TDM link, with potential scalability to 100 Gbps. Such aggressive link rates place severe requirements on switch architecture, particularly the buffering scheme. In this paper we present the ATM switch structure and justify the main design choices.

An efficient adaptive bus arbitration scheme for scalable shared-medium ATM switch

Since the asynchronous transfer mode (ATM) has been strongly promoted as the transport structure for broadband integrated services digital networks, a variety of ATM switching architectures have been proposed. The knockout switch, which is one of the well known ATM switches, has a single-stage architecture and adopts an output buffering method. It has excellent traffic performance (cell loss probability, maximum throughput and delay, etc.), but needs many switch elements and buffers. The authors propose an ATM switch, called a knockout switch with input buffers. The proposed switch has almost the same traffic performance as the existing knockout switch but needs fewer switch elements and buffers than the existing knockout switch. The authors analyse the traffic performance and complexity (i.e. the number of switch elements and buffers required) of the proposed architecture by discrete-time Markov chain models and compare them with those of the existing knockout switch. It is found that the proposed architecture could reduce the need for over 40% of the switch elements and over 30% of the buffers while satisfying the given loss requirements.

In this paper we present our results on formally verifying the implementation of an asynchronous transfer mode (ATM) network switching fabric using a new class of decision graphs, called Multiway Decision Graphs (MDG). The design we consider is in use for real applications in the Cambridge Fairisle network. We produced the description of the hardware implementation at different levels of abstraction. We then performed the verification of an abstract description model against the description of the gate-level implementation. Using this abstract model, we accomplished the verification of specific properties that reflect the behavior of the Fairisle ATM switch fabric.

The large capacity ATM backbone switch “FETEX-150 ESP”

The objective of the paper is to describe a hierarchical network architecture based on all-optical Wavelength Division Multiplexed (WDM) networks extended (for longer distances) through Asynchronous Transfer Mode (ATM) networks. The local subnetworks are designed as all-optical WDM networks that require tunable components and a media access protocol. These networks are designed to efficiently support multimedia traffic and ATM encapsulation is used for local transport. The WDM networks are interconnected using generalized multichannel ATM switches. The ATM switches are termed as generalized since they are designed to utilize multiple wavelengths (provided by WDM) on the input/output links. The wavelengths on each link are allocated to different virtual circuit connections, to send signaling and control information, and to enhance priority handling.

In interconnections between bookshelf-assembled asynchronous transfer mode (ATM) switch boards, a large number of micro-optical signal beams can be optically interconnected by a beam direction compensating system using a vertical cavity surface emitting laser, an x-y beam positioning sensor and a beam deflector made of an adjustable liquid prism. This beam direction compensating system can suppress the decrease in coupling efficiency between transmitters and receivers to no more than 15%, even if boards are inserted and extracted repeatedly, and are shocked repeatedly at a high intensity of 100 G. The compensation is very fast (20 ms). Furthermore, various optical interconnections necessary for ATM switching networks can be achieved by beam deflectors of a liquid crystal microprism array. In this preliminary study, we fabricate no more than eight-channel optical interconnections. However, since one surface emitting laser diode can have many channels in a small area (64 channels per 4 mm/sup 2/) and the aperture of this adjustable liquid prism is wide (28 mm in diameter) and uniform, a huge number of optical interconnection channels is possible using this system.