Performance analysis of input queueing ATM switches with parallel iterative matching scheduling

The performance of a non-blocking ATM switch in which each input port maintains a separate queue for each output port to overcome the head-of-line (HOL) blocking of conventional FIFO input queuing switches is presented. Parallel iterative matching (PIM) is used as the scheduling algorithm for selecting the HOL cells to be transmitted in each time slot. After deriving a closed-form solution for the maximum throughput of the switch under saturated conditions, an analytical model for evaluating the switch performance under i.i.d Bernoulli traffic is developed using the tagged input queue approach. Performance measures including throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.

In this paper, we purpose a novel approach to analyze exact cell loss probability of Shared Buffer ATM switch. In a N X N ATM switch whose input ports and output ports share one buffer, the number of arriving cells from input ports at one time slot is less than or equal to N. If these cells were destined to n output ports, no cells will be destined to the remaining N-n output ports. In the extremism, all arriving cells were destined to one output port, no cell will be destined to the other N-1 output ports. So, the arriving cells at each time slot from the input ports are destined to the output ports correlatively, but not independently. For this reason, the analyzing result on the assumption that all output cell queues are independent one another is larger than actual result. We complete our analysis by three steps. First, considering the case that there are cells arriving from input ports but not cells remove from output ports, we can get one-step state transition probability matrix P<SUB>a</SUB>; Second, considering the case that there are cells removing from output ports but not cells arrive from input ports, we can get one-step state transition probability matrix Ps; Third, considering arrival process and service process are independent, the accurate one-step state transition probability matrix P of cell's number in the buffer is derived, and then cell queue length steady probability distribution can be found. We can compute the accurate buffer capacity below certain cell loss probability. Computer simulation proves that the approach is efficient and exact.

In this letter, we analyze the performance of multiple input-queued asynchronous transfer mode (ATM) switches that use parallel iterative matching (PIM) for scheduling the transmission of head-of-line cells in the input queues. A queueing model of the switch is developed under independently, identically distributed, two-state Markov modulated Bernoulli processes bursty traffic. The underlying Markov chain of the queueing model is a quasi-birth-death (QBD) chain. The QBD chain is solved using an iterative computing method. Interesting performance metrics of the ATM switch such as the throughput, the mean cell delay, and the cell loss probability can be derived from the model. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is briefly discussed.

Port partitioning and dynamic queueing for IP forwarding

The multiple input-queued (MIQ) switch is the switch which manages multiple (m) queues in each input port, each of which is dedicated to a group of output ports. Since each input port can switch up to m cells in a time slot, one from each queue, it hardly suffers from the head-of-line (HOL) blocking which is known to be the decisive factor limiting the throughput of the single input-queued (SIQ) switch. As a result, the MIQ switch guarantees enhanced performance characteristics as the number of queues m in an input increases. However, the service of multiple cells from an input could cause internal speedup or expansion of the switch fabric, diluting the merit of high-speed operation in the conventional SIQ scheme. The restricted rule is contrived to circumvent this side effect by regulating the number of cells switched from an input port. We analyze the performance of the MIQ switch employing the restricted rule. For the switch using the restricted rule, the closed formulas for the throughput bound, the mean cell delay and average queue length, and the cell loss bound of the switch are derived as functions of m, by generalizing the analysis for the SIQ switch by J.Y. Hui and E. Arthurs (see IEEE J. Select. Areas Commun., vol.SAC-5, p.1262-73, 1987).

Output Queuing (OQ) and Input Queuing (IQ) are the two basic queuing strategies implemented in routers. IQ has been identified as the simplest and the most scalable. However, the IQ only achieves 58.6% throughput due to the Head Of Line (HOL) blocking effect. The Virtual Output Queuing (VOQ) strategy is a proffered solution to the HOL blocking. It has been shown that VOQ can achieve a 100% throughput with an effective scheduling algorithm. This paper proposes a Multi stage Queuing and Scheduling architecture in which VOQ is implemented at the input and OQ at the output. The scheduling algorithm for the VOQ presented in this paper is an Iterative Probabilistic Scheduling.

This paper is about high capacity switches and routers that give guaranteed throughput, rate and delay guarantees. Many routers are built using input queueing or combined input and output queueing (CIOQ), using crossbar switching fabrics. But such routers require impractically complex scheduling algorithms to provide the desired guarantees. We explore how a buffered crossbar-a crossbar switch with a packet buffer at each crosspoint-can provide guaranteed performance (throughput, rate, and delay), with less complex, practical scheduling algorithms. We describe scheduling algorithms that operate in parallel on each input and output port, and hence are scalable. With these algorithms, buffered crossbars with a speedup of two can provide 100% throughput, rate, and delay guarantees.

In this paper, we propose the use of the Bidirectional Manhattan Street Network (BMSN) for interconnecting fixed size switching modules into a large scale ATM switch. Using BMSN for this purpose, each node now becomes an ATM switching module with its own input and output ports, and with four extension trunks connecting to four neighbouring modules. In this way, the switch size and capacity can increase by adding switching modules in a stepwise and planar manner, and there is no need for rewiring the I/O ports and the internal links. We extend BMSN into another architecture called SpiderNet, which connects eight instead of four neighbours. The average path length is reduced by having more direct paths. SpiderNet gives a better call blocking performance and cell loss probability, hence has a higher switch capacity. We show how routing paths can be established, and how cells are self-routed through the interconnected fabric. Cell loss and delay performance is also discussed.

ATM communication systems have introduced a number of new dimensioning problems, one being the evaluation of the loss probability for a shared buffer memory within a switch matrix. This is a problem of growing interest since shared buffer memory switches offer the best cell loss probability versus total buffer space provided, and thus are often the design of choice. ATM switches operate in a time slotted fashion: at the end of each slot, N cells will have been transmitted if all N servers have cells for transmission. If a server has no cell to transmit, it will produce an empty slot. Iliadis (1991) has presented a method for solving such a system based on the introduction of an N dimensional Markov chain. Schormans et al. (see Electronics Letters, vol.30, no.1, 1994) have presented a simplified algorithm for a fairly general arrival process. This paper considers certain problems in (shared) buffer dimensioning: calculation of the cell loss probability (CLP) for a 2/spl times/2 switching element, given any i/p loading; the effect, on such a shared buffer switching element, of allowing the applied traffic to approach the limit, i.e. during each time slot every input line will contain a new cell; and the relationship between the cell loss probability and the model of the routing strategy.

High-speed input queued switches are known to be more economical and simpler than output queued switches. However, they suffer from HOL blocking which degrades throughput significantly. Input queued switches can achieve higher throughput if they use random access input queues and cell scheduling algorithms. Especially, input queued ATM switches employing the cell-scheduling algorithm can increase the throughput by preventing output conflict. A self-firing cell scheduling algorithm in input queued ATM switches has been proposed but it is unfair in the sense that the throughputs from various input ports differ by significant amounts. In this paper, we propose a cell scheduler that has inherent fairness properties under any traffic pattern and prove that the proposed cell scheduler guarantees fairness even if traffic is not uniform pattern by computer simulation.

Performance analysis of packet switches with input and output buffers

We describe a novel method for scheduling highspeed network switches. The targeted architecture is an input-buffered switch with a non-blocking switch fabric. The input buffers are organized as virtual output queues to avoid head-of-line blocking. The task of the scheduler is to decide when the input ports can forward packets from the virtual output queues to the corresponding output ports. Our Least Choice First (LCF) scheduling method selects the input and output ports to be matched by prioritizing the input ports according to the number of virtual output queues that contain packets: The fewer virtual output queues with packets, the higher- the scheduling priority, of the input port. This way the number- of switch connections and, with it, switch throughput is maximized. Fairness is provided through the addition of a round-robin algorithm. We present two alternative implementations: A central implementation intended for narrow, switches and a distributed implementation based on an iterative algorithm intended for wide switches. The simulation results show that the LCF scheduler outperforms other scheduling methods such as the parallel iterative matcher, iSLIP, and the wave front arbiter.

We study a basic problem in Multi-Queue switches. A switch connectsm input ports to a single output port. Each input port is equipped with an incoming FIFO queue with bounded capacityB. A switch serves its input queues by transmitting packets arriving at these queues, one packet per time unit. Since the arrival rate can be higher than the transmission rate and each queue has limited capacity, packet loss may occur as a result of insufficient queue space. The goal is to maximize the number of transmitted packets. This general scenario models most current networks (e.g. IP networks) which only support a “best effort” service in which all packet streams are treated equally. A 2-competitive algorithm for this problem was designed in [5] for arbitraryB. Recently, a (17/9 ≈ 1.89)-competitive algorithm was presented forB>1 in [3]. Our main result in this paper shows that forB which is not too small our algorithm can do better than 1.89, and approach a competitive ratio ofe/(e − 1) ≈ 1.58.

High speed variable length packet switches often use a cell switching core. For such purposes, an input queueing structure has an advantage since it imposes minimal bandwidth requirements on cell buffering memories; this leads to superior scalability of switches. The authors consider input queueing switches in which all cells arriving at an input are queued in a single first-come-first-served queue. It is well known that, for such a simple arrangement, the maximum switch throughput can be obtained by a saturation analysis (i.e. each queue is assumed to be infinitely backlogged and then the switch throughput is computed). The authors establish that this saturation throughput also provides a sufficient condition for stochastic stability of the input queues. It is assumed that the cell arrival process at each input is Bernoulli. Each input belongs to one of two priority classes; during output contention resolution, the head-of-the-line cell from a high priority input is given preference. The saturation throughputs of the high and low priority inputs can be computed. It is proved that if the arrival rate at each input is less than the saturation throughput then the queue lengths are stochastically stable. The major contribution of the paper is that it provides an analytical approach for such a problem; the technique can be adapted for more general problems.