ASF: a practical simulation-based methodology for the synthesis of custom analog circuits

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CADsEDA industry professionals, academics and students.

Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm

When ICCAD began in 1983, we had no robust tools for device modelling, analog circuit synthesis, electrical timing simulation, transistor-to-logic abstraction, or large-scale custom circuit tuning. Today, all these techniques are in common industrial usage, most commercially available. The seven papers in this section fundamentally transformed the way in which we model, manipulate, and solve these difficult tasks today. They are linked by a common thread of “deep circuits innovation”.

Accurate performance modeling is essential for its usage in a circuit synthesis flow. Only a small fraction of the entire design space is occupied by designs with meaningful behavior and performance. In this work, we have focussed on modeling these feasible regions accurately in contrast with modeling the entire design space. Macromodels for the feasible regions were built hierarchically until the desired accuracy was achieved. An accuracy driven synthesis methodology is proposed to guide the identification of the feasible regions and dynamically enhance the performance of the macromodels. Dynamic performance modeling ensures true convergence of our synthesis approach as opposed to existing static macromodel based techniques. We applied the proposed methodology for modeling and synthesis of several analog and RF circuits and the results demonstrate that our approach yields highly accurate design solutions in a much smaller time compared to simulation based approaches.

In this article, a novel field-programmable analog array (FPAA) has been developed for the configurable implementation of various analog circuits. The proposed architecture not only supports system-level reconfiguration but also enables transistor-level programmability. The FPAA is comprised of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times 4$</tex-math> </inline-formula> configurable analog block (CAB) array, with a single configurable logic block (CLB) added to each column to allow for the programming of digital circuits. Passive devices, including programmable capacitors and resistors, and active transistor pairs (TPs), are utilized to implement both continuous-time and discrete-time circuits. A placement algorithm is developed that efficiently maps analog circuits onto the FPAA fabric by finding the optimal vertical and horizontal locations for the assignment of transistors. In addition, to reduce the complexity of placing devices on the fabric, a technique is developed that matches TPs in the same vertical level to predefined topologies in a library. Routers are included to connect devices implemented on the FPAA fabric. The proposed FPAA occupies an area of 4 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a TSMC 65-nm fabrication process. The smaller circuits implemented on the FPAA fabric include a folded-cascode amplifier, a strongArm comparator, a continuous-time integrator, and a switch-capacitor integrator. The larger analog and mixed-signal circuits implemented on the FPAA fabric include a four-stage pipeline analog-to-digital converter (ADC) and a first-order delta-sigma modulator. The programmed folded-cascode amplifier exhibits a tunable gain of 28.3 dB to 34.8 dB and a programmable 3-dB bandwidth of 3.3 MHz to 5.3 MHz. The configured comparator provides a resolution of less than 3 mV when comparing two signals. The implemented first-order delta-sigma modulator operates at a frequency of 15 MHz and provides an effective number of bits (ENOBs) of 6.8 when utilizing an oversampling ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$128\times $</tex-math> </inline-formula>. The configured pipeline ADC provides an ENOB of 3.7 for a sampling frequency of 15 MHz.

Evolvable Hardware (EHW) applications have, so far, encompassed the synthesis of standard analog and digital circuits' building blocks through Genetic Algorithms (GAs). Currently, the research effort in EHW is being driven towards twofold purposes: the synthesis of circuits of medium to high complexity; and the design of reconfigurable architectures that facilitate the system evolvability and on-chip implementation of the evolved circuits. This work addresses these issues by describing the evolution of Digital to Analog Converters (DACs). We investigate the efficiency of the evolutionary system when using different representations and when evolving current and voltage mode circuits. A new technique based on hierarchical evolution is devised to enhance the evolutionary speed and the design scalability. New methods to increase the competitiveness of the evolved designs are also discussed.

Fault identification of analog and mixed signal circuits is very difficult topics for previous few decades. Localization of hard and soft faults in analog circuit is often a troublesome task without a transparent cut methodology. For manufacturing process of Very Large Scale Integration (VLSI) Application Specific Integrated Circuits (ASICs) both fault diagnosis and localization are mandatory. The importance of such analog test has become important due to enhancement of networking and communication sector. This paper gives a brief review on the faults present in analog circuits and different diagnosis methodologies of these faults. Comparison of detection is also demonstrated among some techniques for some of the ITC97 Benchmark circuits.

Problem statement: Day by day more and more products rely on analog circuits to improve the speed and reduce the power consumption(Products rely on analog circuits to improve the speed and reduce the power consumption day by day more and more.). For the VLSI implementation analog circuit design plays an important role. This analog circuit synthesis might be the most challenging and time-consumed task, because it does not only consist of topology and layout synthesis but also of component sizing. Approach: A Particle Swarm Optimization (PSO) technique for the optimal design of analog circuits. Analog signal processing finds many applications and widely uses OpAmp based amplifiers, mixers, comparators. and filters. Results: A two-stage opamp (Miller Operational Trans-conductance Amplifier (OTA)) is considered for the synthesis that satisfies certain design specifications. Performance has been evaluated with the Simulation Program with Integrated Circuit Emphasis (SPICE) circuit simulator until optimal sizes of the transistors are found. Conclusion: The output of the simulation for the two-stage opamp shows that the PSO technique is an accurate and promising approach in determining the device sizes in an analog circuit.

During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.

The nullor, as a network element, is very popular in the areas of modeling, synthesis and analysis of analog circuits. Nullors are pathological or singular elements that posses ideal characteristics and are specified according to the constraints they impose on their terminal voltages and currents. Therefore, in order to compute symbolic expressions of pathological element-base equivalent analog circuits, the nullor properties should be taken into account in the formulation process. Nodal analysis (NA) of these circuits is very popular. However, the recently proposed methods of formulation the nodal admittance (NA) matrix, require many operations on the rows and columns of an initial node admittance matrix (INAM), which has the order (nxn), for the (n+1) node network or a laborious procedure of computation of norator and nullator indexes. This paper presents a new method of formulation of the nodal admittance matrix for linear active circuits with nullors that performs direct construction of the final nodal admittance matrix (FNAM), which has the order (n-k)x(n-k), and uses only classical methods of element stamps. (k is the number of nullators and norators pairs). The viability and the potentiality of the proposed method (of the FNAM) is showcased via application examples. The improved formulation method is compared with other formulation methods, showing that it is simpler.

Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evolving digital systems by directly mapping a chromosome on the FPGA configuration bitstream. This approach allowed a great degree of flexibility for evolving circuits. Nowadays, FPGAs routing scheme does not allow doing it in such flexible and safe way, so additional constraints must be introduced. In this paper we summarize three techniques for performing hardware evolution by exploiting the capacities of Virtex families. Among our proposals there are high and low level approaches, and coarse and fine grained components. A modular based evolution, with pre-placed and routed components, provides a coarse grain approach. Two techniques for directly modifying LUT contents on hard macros provide a fine grained evolution. Finally, integrating both approaches, coarse and fine grain, provides a more general and powerful framework.

A prototype system to aid analog design engineers in the synthesis and analysis of CMOS analog circuits has been developed. ACAD (analog computer-aided design) differs from other tools by its extensive use of hierarchy and two-port network theory to subdivide the process of solving the small signal network functions. This allows larger circuits to be analyzed. ACAD solved and simplified all of the two-port network equations for an operational amplifier containing 29 MOS transistors, 2 resistors, and 3 capacitors by analyzing, simplifying, and combining four subcircuits. ACAD produced the correct results for the model being evaluated. These results show that computer-aided hierarchical small signal model analysis of analog circuits is possible.

Analog test represents an increasing fraction of the cost of producing analog and mixed-signal integrated circuits. While digital testing can focus on identifying spot defects a systematic manner, analog functional testing requires very precise and accurate measurements. Pessimistic forecasts suggest that in the next few years the total product cost of a mixed-signal device will be almost entirely due to the cost of the analog tests. The LEMMA method is a model-based approach to minimizing the analog test effort by identifying a robust minimum set of testpoints.

Efficient high-dimensional performance modeling of nanoscale analog and mixed signal (AMS) circuits is extremely challenging. In this paper, we propose a novel structure-aware modeling (SAM) technique. The key idea of SAM is to accurately solve the model coefficients by applying an efficient statistical algorithm to exploit the underlying structure of AMS circuits. As a result, SAM dramatically reduces the required number of sampling points and, hence, the computational cost for performance modeling. Several circuit examples designed in a commercial 32nm CMOS process demonstrate that SAM achieves more than 2× runtime speedup over the traditional sparse regression technique without surrendering any accuracy.

Introduction Mixed-signal integrated circuits (ICs) for sensor signal conditioning are widely used today in sensor applications such as pressure, temperature and position monitoring. In these signal conditioners, the conditioning of the output signal from the sense element is performed with mixed-signal circuits, which are a combination of analog and digital circuits. Moreover, the actual conditioning of the sense-element signals is implemented in the digital domain. The conditioned signal is the output of the sensor signal conditioner. The sensor output is transmitted to a control or monitoring system either in analog or digital form. If an analog form of transmission is used, the processed digital signal must be converted back to analog form. This article examines the calibration of sensor signalconditioning algorithms implemented in signal conditioners that transmit data in analog form. Note that sensor calibration includes the sense-element non-idealities as well as signal-conditioner non-idealities, such as offset and gain errors. The calibration scheme will take care of analog signal-chain errors of the analog circuit that are in front and back of the digital circuits.