Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs

Evolvable Hardware (EHW) applications have, so far, encompassed the synthesis of standard analog and digital circuits' building blocks through Genetic Algorithms (GAs). Currently, the research effort in EHW is being driven towards twofold purposes: the synthesis of circuits of medium to high complexity; and the design of reconfigurable architectures that facilitate the system evolvability and on-chip implementation of the evolved circuits. This work addresses these issues by describing the evolution of Digital to Analog Converters (DACs). We investigate the efficiency of the evolutionary system when using different representations and when evolving current and voltage mode circuits. A new technique based on hierarchical evolution is devised to enhance the evolutionary speed and the design scalability. New methods to increase the competitiveness of the evolved designs are also discussed.

When ICCAD began in 1983, we had no robust tools for device modelling, analog circuit synthesis, electrical timing simulation, transistor-to-logic abstraction, or large-scale custom circuit tuning. Today, all these techniques are in common industrial usage, most commercially available. The seven papers in this section fundamentally transformed the way in which we model, manipulate, and solve these difficult tasks today. They are linked by a common thread of “deep circuits innovation”.

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CADsEDA industry professionals, academics and students.

Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm

Accurate performance modeling is essential for its usage in a circuit synthesis flow. Only a small fraction of the entire design space is occupied by designs with meaningful behavior and performance. In this work, we have focussed on modeling these feasible regions accurately in contrast with modeling the entire design space. Macromodels for the feasible regions were built hierarchically until the desired accuracy was achieved. An accuracy driven synthesis methodology is proposed to guide the identification of the feasible regions and dynamically enhance the performance of the macromodels. Dynamic performance modeling ensures true convergence of our synthesis approach as opposed to existing static macromodel based techniques. We applied the proposed methodology for modeling and synthesis of several analog and RF circuits and the results demonstrate that our approach yields highly accurate design solutions in a much smaller time compared to simulation based approaches.

Deep learning-based approaches in histopathology can be largely divided into two categories: a high-level approach using an end-to-end model and a low-level approach using feature extractors. Although the advantages and disadvantages of both approaches are empirically well known, there exists no scientific basis for choosing a specific approach in research, and direct comparative analysis of the two approaches has rarely been performed. Using the Cancer Genomic Atlas (TCGA)-based dataset, we compared these two different approaches in microsatellite instability (MSI) prediction and analyzed morphological image features associated with MSI. Our high-level approach was based solely on EfficientNet, while our low-level approach relied on LightGBM and multiple deep learning models trained on publicly available multiclass tissue, nuclei, and gland datasets. We compared their performance and important image features. Our high-level approach showed superior performance compared to our low-level approach. In both approaches, debris, lymphocytes, and necrotic cells were revealed as important features of MSI, which is consistent with clinical knowledge. Then, during qualitative analysis, we discovered the weaknesses of our low-level approach and demonstrated that its performance can be improved by using different image features in a complementary way. We performed our study using open-access data, and we believe this study can serve as a useful basis for discovering imaging biomarkers for clinical application.

Problem statement: Day by day more and more products rely on analog circuits to improve the speed and reduce the power consumption(Products rely on analog circuits to improve the speed and reduce the power consumption day by day more and more.). For the VLSI implementation analog circuit design plays an important role. This analog circuit synthesis might be the most challenging and time-consumed task, because it does not only consist of topology and layout synthesis but also of component sizing. Approach: A Particle Swarm Optimization (PSO) technique for the optimal design of analog circuits. Analog signal processing finds many applications and widely uses OpAmp based amplifiers, mixers, comparators. and filters. Results: A two-stage opamp (Miller Operational Trans-conductance Amplifier (OTA)) is considered for the synthesis that satisfies certain design specifications. Performance has been evaluated with the Simulation Program with Integrated Circuit Emphasis (SPICE) circuit simulator until optimal sizes of the transistors are found. Conclusion: The output of the simulation for the two-stage opamp shows that the PSO technique is an accurate and promising approach in determining the device sizes in an analog circuit.

Great achievements in the area of evolvable hardware have been reported in the last decade. Evolvable hardware comprises an evolutionary algorithm, such as a genetic algorithm, and a reconfigurable hardware, such as field programmable analog arrays and field programmable gate arrays. In these devices, internal circuits' connections can be programmed for specific applications. In this paper, configurability and evolvability issues are addressed in the domain of synthesis of analog circuits on an analog reconfigurable platform. First, implementation aspects and characteristics are presented: then some circuits' syntheses are discussed. Finally the authors present their view on how the techniques and approaches studied in the domain of the synthesis of analog circuits could be extended and applied in other domains, such as molecular electronics.

Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments on selected applications, and presents a perspective on the development of the field. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. These characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life. Expanding reconfiguration to other types of spacecraft hardcore (i.e. optics, MEMS, etc.) could lead to evolvable space systems.

This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufacturing process. To manage complexity and time-to-market, SoC designs require a high level of automation and reuse. Digital methodologies are inapplicable to analog IP, which relies on tight control of low-level device and circuit properties that vary widely across manufacturing processes. This analog synthesis solution automates these tedious, technology specific aspects of analog design. Unlike previously proposed approaches, ASF extends the prevalent and SPICE methodology used to design analog and mixed-signal circuits. ASF is topology and technology independent and can be easily integrated into a commercial schematic capture design environment. Furthermore, ASF employs a novel numerical optimization formulation that incorporates classical downhill techniques into stochastic search. ASF consistently produces results comparable to expert manual design with 10/spl times/ fewer candidate solution evaluations than previously published approaches that rely on traditional stochastic optimization methods.

During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.

The ability to live migrate virtual machines (VMs) between physical servers without any perceivable service interruption is pivotal for building more energy efficient Cloud Computing infrastructures in the future. Nevertheless, energy efficiency is not worth the effort if quality metrics (e.g., QoS, QoE) are severely decreased by, e.g., dynamic consolidation using live migration. In this work, we present results for a low level approach by patching KVM to implement Xen's live migration stop conditions, and a high level approach by monitoring the progress and service level state of a live migration and estimating the impact on the service level during the remaining migration time. We compare these approaches with an unpatched, vanilla KVM version and different sets of parameters used for live migration. Our service level management approaches offer superior QoS during migration. Especially, they allow to migrate also highly utilized VMs with comparably small influence on QoS.

The nullor, as a network element, is very popular in the areas of modeling, synthesis and analysis of analog circuits. Nullors are pathological or singular elements that posses ideal characteristics and are specified according to the constraints they impose on their terminal voltages and currents. Therefore, in order to compute symbolic expressions of pathological element-base equivalent analog circuits, the nullor properties should be taken into account in the formulation process. Nodal analysis (NA) of these circuits is very popular. However, the recently proposed methods of formulation the nodal admittance (NA) matrix, require many operations on the rows and columns of an initial node admittance matrix (INAM), which has the order (nxn), for the (n+1) node network or a laborious procedure of computation of norator and nullator indexes. This paper presents a new method of formulation of the nodal admittance matrix for linear active circuits with nullors that performs direct construction of the final nodal admittance matrix (FNAM), which has the order (n-k)x(n-k), and uses only classical methods of element stamps. (k is the number of nullators and norators pairs). The viability and the potentiality of the proposed method (of the FNAM) is showcased via application examples. The improved formulation method is compared with other formulation methods, showing that it is simpler.

A prototype system to aid analog design engineers in the synthesis and analysis of CMOS analog circuits has been developed. ACAD (analog computer-aided design) differs from other tools by its extensive use of hierarchy and two-port network theory to subdivide the process of solving the small signal network functions. This allows larger circuits to be analyzed. ACAD solved and simplified all of the two-port network equations for an operational amplifier containing 29 MOS transistors, 2 resistors, and 3 capacitors by analyzing, simplifying, and combining four subcircuits. ACAD produced the correct results for the model being evaluated. These results show that computer-aided hierarchical small signal model analysis of analog circuits is possible.

Evolvable hardware(EHW) refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment, and ant colony optimization is a meta-heuristic algorithm for the approximate solution of combinatorial optimization problems that has been inspired by the foraging behavior of real ant colonies. In this paper, we take a broad view on the progresses of ant colony optimization-based EHW, which include ant colony optimization-based random number generator, FPGA implementation, digital circuits, digital IIR filters and so on. Some important issues of the challenges of ant colony optimization-based EHW are also presented, and online realization, robustness, generalization, disaster problem are four key challenging issues of ant colony optimization-based EHW in the future