Aspects of memory hierarchy concepts extended to microcode-store level

Research on artificial neural networks (ANNs) has been carried out for more than five decades. A renewed interest appeared in the 80's with the finding of powerful models like J. Hopfield's recurrent networks, T. Kohonen's self-organizing feature maps, and the back-propagation rule. At that time, there was no platform that was at the same time versatile enough for any ANN model to be implemented and fast enough to solve large problems. Super-computers were the sole exception to this rule, but were prohibitively expensive for most applications. However, both research scientists and application engineers clearly identified the need for such a computing power. This triggered many projects in the field. In parallel, research on multi-processor systems started during the 60's. Systolic arrays have been proposed in 1979 as a means to fully exploit the possibilities of VLSI. Two previous theses, by F. Blayo and C. Lehmann, have studied the use of bi-dimensional systolic arrays for neural computation. At first, the presented system, called GENES, has been designed for the Hopfield model. Extensions to other ANNs have also been proposed. The goal of the present thesis is to study, design, build, and analyze an efficient accelerator for neural computation. In a first step, the GENES architecture has been extended towards generality and efficiency. This includes a thorough analysis of ANN models, of other neural computers, and of previous GENES implementations. The result of this work is the GENES IV integrated circuit, whose architecture has been co-designed by P. Ienne and the author. The main part of this thesis discusses the architecture, the design and the analysis of the MANTRA I machine, a neural computer based on a GENES IV array with up to 40 × 40 processing elements (PEs). The delta rule (and hence the Perceptron and Adaline rules), the back-propagation rule, the Hopfield model, and the Kohonen model can be implemented on this system. Although not a generic system, such a machine may be regarded as a multi-model neural computer. A prototype has been running for a year and is used daily by software designers. Several novel features distinguish the MANTRA I machine from other neural systems. First, it belongs to the few existing neural computers, contrary to the majority of implementations, which are specific to an application or to an algorithm. The machine does not hard-wire any algorithm, but provides the necessary primitives to implement the target models. This is a key feature for research, since several algorithms or versions of an algorithm can be tested on a problem. It is an important aspect for applications as well, because different ANN models are often cascaded to solve a problem. The GENES IV array — that is, the computing core of the MANTRA I machine — features synapse-level parallelism (i.e., one real or virtual PE is allocated per synapse or neural connection), while most other systems exploit only neuron-level parallelism (i.e., one PE per neuron). Hence, this system aims at a much finer parallelism grain and is well suited for massively parallel architectures. The problem size that can be computed by a neural accelerator should not be limited by the hardware (except for memory size). Therefore, it is essential to support time-sharing of PEs. On the MANTRA I machine, this is achieved by the concept of virtual arrays. Matrices are divided into sub-matrices that can be mapped onto the physical array, which is then time-shared among them. An efficient mechanism has been implemented to swap sub-matrices in background, while some other computation is performed. Since systolic arrays are pipelined systems, it is important to avoid emptying and re-filling them too often, in order to keep the hardware utilization rate high. Therefore, a systolic instruction flow has been implemented, so that each instruction follows the data for which it has been issued. Like any SIMD system, the MANTRA I machine is composed of a parallel or SIMD module and a control module. The SIMD module consists of the GENES IV array and a set of dedicated units designed for the computation that scales with the number of neurons and would poorly fit on a bi-dimensional array. A complex system of FIFOs and memories sustains the required input/output streams for the systolic array. The control module is a complete SISD system. Its tasks are (1) to control the SIMD module by dispatching instructions, (2) to manage data input and output, (3) to communicate with the external world, and (4) to perform data pre- and post-processing. The SIMD instructions are of the very long instruction word (VLIW) type. Synchronization between the two modules is achieved by an instruction FIFO. The performance of the MANTRA I machine has been analyzed using the delta rule. Measurements show that the sustained performance is very close to its peak value, as long as the problem fits in the memory banks connected to the GENES IV array. Experiments have also been run to investigate the impact of the constraints imposed by the hardware on the convergence of algorithms. Finally, the use of systolic arrays as neural accelerators is discussed in the light of the experience acquired with the GENES IV array and the MANTRA I machine. The weaknesses of the machine are analyzed, and several solutions are proposed to avoid them in a future design. A general discussion of the future of neural computers concludes this thesis.

When it comes to performance, embedded systems share many problems with their higher-end counterparts. The growing gap between top processor frequency and memory access speed, the memory wall, is one such problem. Driven, in part, by low energy consumption and low cost requirements, embedded systems are often customized to a single application, or a very small set of applications. In addition, time-to-market requirements and the increasing complexity of embedded systems drives the need for fully or partially automated design tools and also to the extensive use of caches and cache hierarchies. The introduction of multi-processor-based embedded platforms has accelerated this trend; as the design space for embedded systems has grown, designers have become unclear as to whether automatic processor customization tools can cope with this increased complexity. The recent introduction of new techniques addressing the automatic customization, such as Architecturally Visible Storage (AVS) memory-enhanced Instruction Set Extension (ISE) identification algorithms, has also created new challenges. AVS memories are distinct from the cache hierarchy and rely on Direct Memory Access (DMA) transfers to communicate with main memory. In an embedded system containing hardware-managed caches, these extra AVS memories, in combination with their corresponding DMA transfers, cause coherence and consistence problems. Although the problems of coherence and consistence are well known in multi-processor systems, conventional solutions may be expensive in terms of area and power consumption, rendering them unacceptable for use in embedded systems. This thesis presents two low cost coherence mechanisms that solve these two problems. The first mechanism addresses embedded systems that already contain a hardware coherence protocol, like many high-end embedded multi-processor systems. Traditionally, the DMA transactions are transparent to the hardware coherence protocol. By ensuring visibility of these DMA transactions to the hardware coherence protocol, coherence can be guaranteed between AVS memories and data cache(s). As a result, minor changes to the DMA engine are required. Moreover, by forcing the processor pipeline to stall if a DMA transfer is active, memory consistence can be guaranteed. This mechanism provides significant speedup when compared to the execution of a non-ISE-enhanced system; however, due to the increase in bus traffic, this speedup comes at the expense of an increase in energy consumption. Coherent and Speculative DMA are both implementations of this mechanism. Single-processor systems do not contain hardware coherence protocols, and would therefore benefit from a lower-cost solution to the coherence and consistence problems than a hardware coherence protocol. By tightly coupling the AVS memories to the hardware cache, coherence and consistence for the complete system can be guaranteed. This coupling requires insignificant changes to the hardware cache's hit detection circuitry and state machine without influencing its critical path, thus it is inherently inexpensive. This mechanism provides significant speedups and reduces the energy consumed if compared to the execution on non-ISE-enhanced systems. Furthermore, the tight coupling enables direct communication between the AVS memories and the data cache, making this mechanism independent from the processor-to-memory distance. Virtual Ways and Way Stealing are both implementations of this mechanism. Besides enforcing coherence and consistence, the ability to integrate the architectural changes into an automated design flow is important. This thesis shows the influence of Coherent DMA, Speculative DMA, Virtual Ways, and Way Stealing on the ISE-identification algorithm. It shows the architectural requirements and the cost for enforcing coherence and consistence that need to be taken into account when applying these mechanisms in an automated flow without formulating new algorithms.

Electromagnetic Environment Associated with Lightning Strikes to Tall Strike Objects

According to the literature, long-term memory disorders appear earliest as mild cognitive impairment progresses to Alzheimer’s disease. Other types of memory impairment are discussed sparcely in literature, most studies include general tests of memory performance. Objective: Compare memory disorders in amnestic mild cognitive impairment and Alzheimer’s disease. Subjects: 75 patients were tested twice in the period of one year, 44 of those with amnestic mild cognitive impairment and 12 with Alzheimer’s disease. Method: Memory disorders were tested using 10 Word Test, Backwards Digit Span, Associative Memory Test, and Rey- Osterrieth Complex Figure Test. Results: Estimate means of associative and visual memory corresponds the norm; disorders appear in domains of short-term memory, working memory, long-term memory, and maximal retrieval in amnestic mild cognitive impairment. All memory domains are below norm in Alzheimer’s disease. Statistically significant mean differences (p < 0,05) were obtained in such domains as short-term memory, maximal retrieval, associative and working memory when comparing the groups of amnestic mild cognitive impairment and Alzheimer’s disease. The level of disturbance is significantly lower in all memory domains in single-domain amnestic mild cognitive impairment than those of Alzheimer’s disease. In multiple-domain amnestic mild cognitive impairment, significantly lower memory disturbances appear only in maximal retrieval (p = 0,026) and working memory (p = 0,001) domains. Conclusions: Disorders in all memory domains – i.e., short-term, working, associative, long-term, visual memory, and maximal retrieval – are characteristic to Alzheimer’s disease. Disorders of short-term, working, long-term memory, and maximal retrieval are characteristic to amnestic mild cognitive impairment. Disorders of memory in multiple-domain amnestic mild cognitive impairment display similar pattern to those in Alzheimer’s disease. It can be assumed that single-domain amnestic mild cognitive impairment progresses to multiple-domain amnestic mild cognitive impairment, as mild cognitive impairment progresses to Alzheimer’s disease. Article in Lithuanian doi:10.5200/sm-hs.2012.114

Nowadays you can see everyone holding mobile phones on the street, used to be with only purely voice service till now, as the progress of the technology, function of wireless internet surfing is more and more valued. Whether video call, on-line browsing, or navigation is to provide consumer a multiple service. To fulfill most users’ request, high-speed downloading of 3G broadband system is needed. Telecom Operators start to create mass HSPA (High Speed Packet Access) system in 2009, meaning HSDPA (High Speed Downlink Packet Access) could reach 14.4Mbps and HSUPA (High Speed Uplink Packet Access) could reach 2Mbps. In order to fulfill this mass transportation, Telecom Operator not only has to upgrade the software and hardware of base stations (aka. Node B), the flow of physical circuit’s transmission also has to reach certain bandwidth. Considering investment cost and quality of service, fixed Telecom operators has take a new generation NG-SDH (Next Generation-Synchronous Digital Hierarchy). Using Ethernet to provide physical transmission of wireless internet browsing. This thesis is mainly discussing new generation Ethernet NG-SDH’s usage, while current base station using physical fiber circuit to provide transmission internet service quality. Through the result if the experiment, we will have a better reference for transmission service quality and solution when future operators planning transmission of HSPA+, 4G LTE (Long Term Evolution).

Described is a display sub-system, designed for support of a very high speed rendering engine. It provides high-performance graphics to an enVironment that consists of a hierarchy of resizable windows. The concept of virtual memory has been applied with the organization of the virtual to physical address spaces having a unique mapping that fits the organization of a bit-mapped graphics memory display.

Non-volatile memories (NVM) including flash memories and resistive memories have attracted significant interest as data storage media. Flash memories are widely employed in mobile devices and solid-state drives (SSD). Resistive memories are promising as storage class memory and embedded memory applications. Data reliability is the fundamental requirement of NVM as data storage media. However, modern nano-scale NVM suffers from challenges of inter-cell interference (ICI), charge leakage, and write endurance, which threaten the reliability of stored data. In order to cope with these adverse effects, advanced coding techniques including soft decision decoding have been investigated actively. However, current coding techniques do not capture the physical properties of NVM well, so the improvement of data reliability is limited. Although soft decision decoding improves the data reliability by using soft decision values, it degrades read speed performance due to multiple read operations needed to obtain soft decision values. In this dissertation, we explore coding schemes that use side information corresponding to the physical phenomena to improve the data reliability significantly. The side information is obtained before writing data into memory and incorporated during the encoding stage. Hence, the proposed coding schemes maintain the read speed whereas the write speed performance would be degraded. It is a big advantage from the perspective of speed performance since the read speed is more critical than the write speed in many memory applications. First, this dissertation investigates the coding techniques for memory with stuckat defects. The idea of coding techniques for memory with stuck-at defects is employed to handle critical problems of flash memories and resistive memories. For 2D planar flash memories, we propose a coding scheme that combats the ICI, which is a primary challenge of 2D planar flash memories. Also, we propose a coding scheme that reduces the effect of fast detrapping, a degradation factor in 3D vertical flash memories. Finally, we investigate the coding techniques that improve write endurance and power consumption of resistive memories.

Background/Objectives: To analyze the caching strategies used in distributed system and techniques involved in scheduling. Methods/Statistical Analysis: System with two or more processor when working simultaneously has the demand over the processing speed in distributed system for sharing the hard disk, memory and other memory devices. A CACHE memory or computer memory with very short access time used for storage of frequently used instruction or data. An extreme fast memory is built into CPU or located next to the chip. Findings: The major possible vulnerabilities over dirty data and cache coherence are also discussed. Many implementations are done for estimating the usage of hardware cache over Distributed real time and embedded system. Various real time applications are integrated with DRE system to reduce the execution time based on optimization techniques. Applications/Improvements: In this paper various techniques over cache with shared multi-processor system covers to reduce the average data access time with various inputs as workload application to check the performance of the system over different cache levels.

In complementary metal–oxide–semiconductor (CMOS) high-speed buffer design, leakage power dissipation, complex routing area, and low-power consumption are the most common challenges. To overcome these challenges, the BiCMOS technology and CMOS multi-valued logic (MVL) are used to maintain the yield and the performance of the high-speed buffers. In this paper, performance comparison of different types of buffers: Schmitt trigger, tristate and bidirectional buffer with BiCMOS and CMOS MVL logic are presented. Cadence virtuoso editor and ADE spectre simulator at gpdk 180 nm technology node are used for simulation setup. The results show that CMOS MVL logic delay, power dissipation, low and high noise margin are better than BiCMOS by 20, 43, 19, and 39%, respectively. Based on these results, CMOS MVL logic outperforms BiCMOS for low-power applications at comparable speed.

As a new medium for questionnaire delivery, the internet has the potential to revolutionise the survey process. Online (web-based) questionnaires provide several advantages over traditional survey methods in terms of cost, speed, appearance, flexibility, functionality, and usability [1, 2]. For instance, delivery is faster, responses are received more quickly, and data collection can be automated or accelerated [1- 3]. Online-questionnaires can also provide many capabilities not found in traditional paper-based questionnaires: they can include pop-up instructions and error messages; they can incorporate links; and it is possible to encode difficult skip patterns making such patterns virtually invisible to respondents. Like many new technologies, however, online-questionnaires face criticism despite their advantages. Typically, such criticisms focus on the vulnerability of online-questionnaires to the four standard survey error types: namely, coverage, non-response, sampling, and measurement errors. Although, like all survey errors, coverage error (“the result of not allowing all members of the survey population to have an equal or nonzero chance of being sampled for participation in a survey” [2, pg. 9]) also affects traditional survey methods, it is currently exacerbated in online-questionnaires as a result of the digital divide. That said, many developed countries have reported substantial increases in computer and internet access and/or are targeting this as part of their immediate infrastructural development [4, 5]. Indicating that familiarity with information technologies is increasing, these trends suggest that coverage error will rapidly diminish to an acceptable level (for the developed world at least) in the near future, and in so doing, positively reinforce the advantages of online-questionnaire delivery. The second error type – the non-response error – occurs when individuals fail to respond to the invitation to participate in a survey or abandon a questionnaire before it is completed. Given today’s societal trend towards self-administration [2] the former is inevitable, irrespective of delivery mechanism. Conversely, non-response as a consequence of questionnaire abandonment can be relatively easily addressed. Unlike traditional questionnaires, the delivery mechanism for online-questionnaires makes estimation of questionnaire length and time required for completion difficult1, thus increasing the likelihood of abandonment. By incorporating a range of features into the design of an online questionnaire, it is possible to facilitate such estimation – and indeed, to provide respondents with context sensitive assistance during the response process – and thereby reduce abandonment while eliciting feelings of accomplishment [6]. For online-questionnaires, sampling error (“the result of attempting to survey only some, and not all, of the units in the survey population” [2, pg. 9]) can arise when all but a small portion of the anticipated respondent set is alienated (and so fails to respond) as a result of, for example, disregard for varying connection speeds, bandwidth limitations, browser configurations, monitors, hardware, and user requirements during the questionnaire design process. Similarly, measurement errors (“the result of poor question wording or questions being presented in such a way that inaccurate or uninterpretable answers are obtained” [2, pg. 11]) will lead to respondents becoming confused and frustrated. Sampling, measurement, and non-response errors are likely to occur when an online-questionnaire is poorly designed. Individuals will answer questions incorrectly, abandon questionnaires, and may ultimately refuse to participate in future surveys; thus, the benefit of online questionnaire delivery will not be fully realized. To prevent errors of this kind2, and their consequences, it is extremely important that practical, comprehensive guidelines exist for the design of online questionnaires. Many design guidelines exist for paper-based questionnaire design (e.g. [7-14]); the same is not true for the design of online questionnaires [2, 15, 16]. The research presented in this paper is a first attempt to address this discrepancy. Section 2 describes the derivation of a comprehensive set of guidelines for the design of online-questionnaires and briefly (given space restrictions) outlines the essence of the guidelines themselves. Although online-questionnaires reduce traditional delivery costs (e.g. paper, mail out, and data entry), set up costs can be high given the need to either adopt and acquire training in questionnaire development software or secure the services of a web developer. Neither approach, however, guarantees a good questionnaire (often because the person designing the questionnaire lacks relevant knowledge in questionnaire design). Drawing on existing software evaluation techniques [17, 18], we assessed the extent to which current questionnaire development applications support our guidelines; Section 3 describes the framework used for the evaluation, and Section 4 discusses our findings. Finally, Section 5 concludes with a discussion of further work.

Polygonal models are ubiquitous in computer graphics but their real time manipulation and rendering especially in interactive application environments have become a threat because of their huge sizes and complexity. A whole family of automatic algorithms emerged during the last decade to help out this problem, but they reduce the complexity of the models uniformly without caring about semantic importance of localized parts of a mesh. Only a few algorithms deal with adaptive simplification of polygonal models. We propose a new model for user-driven simplification exploiting the simplification hierarchy and hypertriangulation model [P. Cignoni et al.] that lends a user the most of the functionalities of existing adaptive simplification algorithms in one place and is quite simple to implement. The proposed new underlying data structures are compact and support real time navigation across continuous LODs of a model; any desirable LOD can be extracted efficiently and can further be fine-tuned. The proposed model for adaptive simplification supports two key operations for selective refinement and selective simplification; their effect has been shown on various polygonal models. Comparison with related work shows that the proposed model provides combined environment at reduced overhead of memory space usage and faster running times.

This thesis examines sexual violence against Jewish women during the Holocaust, as told in testimonies collected in the English language in the Shoah Foundation Institute’s Visual History Archive (hereafter, the Visual History Archive or VHA). It examines the experience of sexual violence, as well as the ways this can be understood through the Visual History Archive. I argue that Jewish women were vulnerable to and experienced sexual violence during the Holocaust in different ways depending on the context in which they found themselves. In this thesis, I explore five of these contexts: the initial Nazi occupation period, in ghettos, in the Nazi camp system, in hiding and during flight, and immediately following the liberation. The thesis begins with a theoretical and methodological consideration of the testimonies and how stories of sexual violence are shaped within the interview. In this section, I firstly consider the Visual History Archive, and the ways that the interviews, the interviewers and the systems of the VHA itself have potentially impacted upon and shaped the English-language interviews that discuss sexual violence. I argue that the origins and conceptual framework of the project, and the ways that the interviews were conducted have an impact on how survivors reveal and discuss issues of sexual violence, as well as on the ability of researchers to investigate sexual violence using this archive. Secondly, I consider the way survivors reflect on their decisions to speak about sexual violence. Survivors often discuss remaining silent, or feeling silenced, about their experiences of sexual violence. In the fifty years between the end of the Holocaust and the recording of the interviews, survivors have been thinking about and attempting to make sense of their memories of sexual violence and how it fits within their Holocaust experience and their life story. The way survivors have interpreted and reinterpreted their experiences of sexual violence influences how they tell these stories in their interviews with the Shoah Foundation. In the remainder of the thesis, I analyse the Visual History Archive’s 989 English-language testimonies that discuss sexual violence and explore five specific contexts of vulnerability in detail. In each context, I identify specific patterns within the interview data, including perpetrators, types of abuse and specific geographic location, and consider how Jewish women were vulnerable in different ways at different points in time and in different contexts of the Holocaust. I also consider factors which potentially influenced the vulnerability of Jewish women, such as anti-Jewish legislation, Nazi laws prohibiting sexual relations between so-called ‘Aryans’ and Jews, and rules and hierarchies within the military and the camp systems that dealt effectively or ineffectively with sexual violence. In this section of the thesis, I argue that Jewish women were vulnerable to sexual violence in different ways depending on the Holocaust context. In sum, in this thesis I examine survivors’ English-language narratives about sexual violence, and how these memories inform historians about the vulnerability of Jewish women and female children during the Holocaust. I argue that the circumstances of Nazi persecution of Jews did not always protect Jewish women from sexual assault, as scholars have previously asserted, but rather the conditions of the Holocaust added a specific gendered layer of vulnerability to sexual violence.

The complexity of integrated circuits requires a hierarchical design methodology that allows the user to divide the problem into pieces, design each piece independently, and assemble the pieces into the complete system. The design hierarchy brings out composition problems, problems that are a property of the assembly as a whole, not of one single instance in the hierarchy. Recent research has produced tools that automate part of the composition task--the logical connection of the pieces. However, these tools do not ensure that signals driven over these connections will be driven sufficiently to give reasonable cycle speed of the resulting chips. It is easily possible to specify an assembly in which a small-sized gate is required to drive an enormous load. Parasitic capacitance of the wiring made automatically by the logical connection tool can be the dominant source of delay, so assembly tools can actually worsen the performance of the circuit and hide this fact from the designer. When required to make large circuits, automated layout tools such as PLA generators can blindly make layouts that give abysmally poor performance. Here again, the delay is in a part of circuit that the designer did not specify, so it is hidden. Finding and correcting these problems is a difficult and time-consuming task in integrated circuit design, and one that consumes vastly more people's time and computer time than the simple assembly of the chip. The task of guaranteeing that circuits meet performance specifications has been left mainly to the designer. Computer aided design has provided analysis tools, tools that tell the designer the performance statistics of the current design. It is then the designer's burden to interpret the performance statistics and use them as guides to make changes in the circuit. This thesis views performance optimization as an electrical composition task. Poor performance as a result of mismatched loads on devices in a problem of composition and should be corrected by the composition tool. Such a tool is presented in this thesis--a program that automatically sizes transistors in a symbolic description of a chip to match the load the transistors are driving. The results are encouraging: they show that delays can be cut by a factor of two in many current designs.

ILP processors can execute a large number of instructions at the same time. Thus it becomes more and more difficult to support traps efficiently. On the other hand a current trend in architecture is to support various memory functions in software rather than hardware, usually by trapping the execution processor on a cache miss, TLB miss or a failed access to a local or remote memory. These late memory traps block the faulting instruction at the top of the active list, backing up the pipeline. Moreover the support for late memory traps may affect the performance of non-faulting memory instructions as well.In this paper we analyze the overhead caused by late memory traps in ILP processors and define several measures for this overhead. In order to tolerate late memory traps, we propose hardware prefetching of exception conditions and a tagged Store buffer to implement deferred traps on Stores. We show that, with these hardware optimizations, the overhead added by the lateness of traps is significantly reduced relative to the overhead of early traps. Because of caching effects the frequency of late memory traps usually decreases as they are taken deeper in the memory hierarchy and their overall impact on the execution time becomes negligible.

Background: It is well known, since the pioneristic observation by Jenkins and Dallenbach (Am J Psychol 1924;35:605-12), that a period of sleep provides a specific advantage for the consolidation of newly acquired informations. Recent research about the possible enhancing effect of sleep on memory consolidation has focused on procedural memory (part of non-declarative memory system, according to Squire’s taxonomy), as it appears the memory sub-system for which the available data are more consistent. The acquisition of a procedural skill follows a typical time course, consisting in a substantial practice-dependent learning followed by a slow, off-line improvement. Sleep seems to play a critical role in promoting the process of slow learning, by consolidating memory traces and making them more stable and resistant to interferences. If sleep is critical for the consolidation of a procedural skill, then an alteration of the organization of sleep should result in a less effective consolidation, and therefore in a reduced memory performance. Such alteration can be experimentally induced, as in a deprivation protocol, or it can be naturally observed in some sleep disorders as, for example, in narcolepsy. In this research, a group of narcoleptic patients, and a group of matched healthy controls, were tested in two different procedural abilities, in order to better define the size and time course of sleep contribution to memory consolidation. Experimental Procedure: A Texture Discrimination Task (Karni & Sagi, Nature 1993;365:250-2) and a Finger Tapping Task (Walker et al., Neuron 2002;35:205-11) were administered to two indipendent samples of drug-naive patients with first-diagnosed narcolepsy with cataplexy (International Classification of Sleep Disorder 2nd ed., 2005), and two samples of matched healthy controls. In the Texture Discrimination task, subjects (n=22) had to learn to recognize a complex visual array on the screen of a personal computer, while in the Finger Tapping task (n=14) they had to press a numeric sequence on a standard keyboard, as quickly and accurately as possible. Three subsequent experimental sessions were scheduled for each partecipant, namely a training session, a first retrieval session the next day, and a second retrieval session one week later. To test for possible circadian effects on learning, half of the subjects performed the training session at 11 a.m. and half at 17 p.m. Performance at training session was taken as a measure of the practice-dependent learning, while performance of subsequent sessions were taken as a measure of the consolidation level achieved respectively after one and seven nights of sleep. Between training and first retrieval session, all participants spent a night in a sleep laboratory and underwent a polygraphic recording. Results and Discussion: In both experimental tasks, while healthy controls improved their performance after one night of undisturbed sleep, narcoleptic patients showed a non statistically significant learning. Despite this, at the second retrieval session either healthy controls and narcoleptics improved their skills. Narcoleptics improved relatively more than controls between first and second retrieval session in the texture discrimination ability, while their performance remained largely lower in the motor (FTT) ability. Sleep parameters showed a grater fragmentation in the sleep of the pathological group, and a different distribution of Stage 1 and 2 NREM sleep in the two groups, being thus consistent with the hypothesis of a lower consolidation power of sleep in narcoleptic patients. Moreover, REM density of the first part of the night of healthy subjects showed a significant correlation with the amount of improvement achieved at the first retrieval session in TDT task, supporting the hypothesis that REM sleep plays an important role in the consolidation of visuo-perceptual skills. Taken together, these results speak in favor of a slower, rather than lower consolidation of procedural skills in narcoleptic patients. Finally, an explanation of the results, based on the possible role of sleep in contrasting the interference provided by task repetition is proposed.