Automotive embedded software: Migration challenges to multi-core computing platforms

Modern computer architectures have evolved from uni-processor platforms to multi-processor and multi-core platforms, but traditional real-time distributed middleware such as RT-CORBA has not kept pace with that evolution. To address those issues, this paper describes the design and implementation of MCFlow, a new real-time distributed middleware for dependent task graphs running on multi-core platforms. MCFlow provides the following contributions to the state of the art in real-time middleware: (1) it provides an efficient C++ based component model through which computations can be configured flexibly for execution within a single core, across cores of a common host, or spanning multiple hosts; (2) it allows optimizations for inter-component communication to avoid data copying without sacrificing the parallel executability of data dependent tasks; (3) it strictly separates timing and functional concerns of an application so that they can evolve and can be configured independently; and (4) it provides a novel event dispatching architecture that uses lock free algorithms to avoid mutex locking and reduce memory contention, CPU context switching, and priority inversion. We also present an empirical evaluation that demonstrates the efficacy of our approach. Type of Report: Other Department of Computer Science & Engineering Washington University in St. Louis Campus Box 1045 St. Louis, MO 63130 ph: (314) 935-6160 The Design and Implementation of MCFlow: a Real-time Multi-core Aware Middleware for Dependent Task Graphs Huang-Ming Huang, Christopher Gill, Chengyang Lu Department of Computer Science and Engineering, Washington University St. Louis, MO, USA {hh1, cdgill, lu}@cse.wustl.edu Abstract—Modern computer architectures have evolved from uni-processor platforms to multi-processor and multi-core platforms, but traditional real-time distributed middleware such as RT-CORBA has not kept pace with that evolution. To address those issues, this paper describes the design and implementation of MCFlow, a new real-time distributed middleware for dependent task graphs running on multi-core platforms. MCFlow provides the following contributions to the state of the art in real-time middleware: (1) it provides an efficient C++ based component model through which computations can be configured flexibly for execution within a single core, across cores of a common host, or spanning multiple hosts; (2) it allows optimizations for inter-component communication to avoid data copying without sacrificing the parallel executability of data dependent tasks; (3) it strictly separates timing and functional concerns of an application so that they can evolve and can be configured independently; and (4) it provides a novel event dispatching architecture that uses lock free algorithms to avoid mutex locking and reduce memory contention, CPU context switching, and priority inversion. We also present an empirical evaluation that demonstrates the efficacy of our approach.Modern computer architectures have evolved from uni-processor platforms to multi-processor and multi-core platforms, but traditional real-time distributed middleware such as RT-CORBA has not kept pace with that evolution. To address those issues, this paper describes the design and implementation of MCFlow, a new real-time distributed middleware for dependent task graphs running on multi-core platforms. MCFlow provides the following contributions to the state of the art in real-time middleware: (1) it provides an efficient C++ based component model through which computations can be configured flexibly for execution within a single core, across cores of a common host, or spanning multiple hosts; (2) it allows optimizations for inter-component communication to avoid data copying without sacrificing the parallel executability of data dependent tasks; (3) it strictly separates timing and functional concerns of an application so that they can evolve and can be configured independently; and (4) it provides a novel event dispatching architecture that uses lock free algorithms to avoid mutex locking and reduce memory contention, CPU context switching, and priority inversion. We also present an empirical evaluation that demonstrates the efficacy of our approach. Keywords-component; middleware

Paper presents brief description of AIIL Controlling System is designed for search and rescue Unmanned Aerial Vehicles (UAV). Concept is result of few years’ development of control systems and was created to fulfill requirements pointed by Red Crescent organization in Iran. This system is a distributed controlling system operates in real-time mode and divides system overhead between stations. Furthermore it is fully customizable and portable that can be used as a platform for advanced navigation systems. Moreover it is a common control system with an open and functional architecture that can be easily added new operational interfaces without any major modifications. The system includes controlling and monitoring parts, flight simulation and also target tracking and flight path planning systems that make the system able to be utilized in real search and rescue missions.

The article deals with the theoretical bases of forming of the government control system of innovative development of Ukraine’s healthcare. It has been found that innovative healthcare processes are slowly developing and need to be resolved. Among the regulatory influences, state regulation is most effective in the field of market transformations.
 The main purpose of the article is to identify the levels of governance and healthcare providers, to group and to characterize the state regulation system of healthcare innovative development.
 The article deals with the levels of hierarchical control (macro level, meso level, micro level, nano level) and the corresponding subjects involved in the process of innovative development of healthcare
 The government control system of innovative development of healthcare can be described as a continuum of functional components, properties of objects, and relations between them in order to achieve primary objectives of innovative development in the sphere. Application of clear and effective tool of government control of innovative development in healthcare is needed for realization of the government control system of innovative development of the aforementioned field and public policy.
 We state, that the signs of the government control system of innovative development of health protection sphere has been distinguished as follows: aims, main reference-point, directions and tasks of government control, general criteria of the government control system of innovative development of healthcare, methods of state stimulation of innovative activity, instruments of government control of innovative development of healthcare, evaluation criteria of instruments of government control.
 We established that the achievement of strategic aims of innovative development of healthcare is impossible without effective government control of innovative processes. Innovative processes are the specific, scale, difficult and many-sided object of adjusting. It requires the use of non-spread functions, methods of influence for effective development of healthcare.

The article describes a structural and functional model of a self-driving car control system, which generates a wide class of mathematical problems. Currently, control systems for self-driving cars are considered at several levels of abstraction and implementation: Mechanics, electronics, perception, scene recognition, control, security, integration of all subsystems into a solid system. Modern research often considers particular problems to be solved for each of the levels separately. In this paper, a parameterized model of the integration of individual components into a complex control system for a self-driving car is considered. Such a model simplifies the design and development of self-driving control systems with configurable automation tools, taking into account the specifics of the solving problem. The parameterized model can be used for CAD design in the field of self-driving car development. A full cycle of development of a control system for a self-driving truck was implemented, which was rub in the “Robocross 2021” competition. The software solution was tested on more than 40 launches of a self-driving truck. Parameterization made it possible to speed up the development of the control system, expressed in man-hours, by 1.5 times compared to the experience of the authors of the article who participated in the same competition in 2018 and 2019. The proposed parameterization was used in the development of individual CAD elements described in this article. Additionally, the implementation of specific modules and functions is a field for experimental research.

Multicore processors are increasingly adopted in resource-constrained real-time embedded applications. In the development of such applications, efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption Threshold Scheduling (PTS) is a well-known technique for controlling the degree of preemption, possibly improving system schedulability, and to reduce system stack usage. In this paper, we consider partitioned multi-processor scheduling on a multicore processor with either Fixed-Priority or Earliest Deadline First scheduling algorithms with PTS and address the design optimization problem of mapping tasks to processor cores and assignment of task priorities and preemption thresholds with the optimization objective of minimizing system stack usage. We present both optimal solution techniques based on Mixed Integer Linear Programming and efficient heuristic algorithms that can achieve high-quality results. We perform extensive performance evaluations using both synthetic tasksets and industrial case studies.

Component based development of software systems needs to devise effective test management strategies in order fully achieve its perceived advantages of cost efficiency, flexibility, and quality in industrial contexts. In industrial systems with quality demands, while testing software, measures are employed to evaluate the thoroughness achieved by execution of a certain set of test cases. Typically, these measures are expressed in the form of coverage of different structural test criteria, e.g., statement coverage. However, such measures are traditionally applicable only on the lowest level of software integration (i.e., the component level). As components are assembled into subsystems and further into full systems, general measures of test thoroughness are no longer available. In this context, we formalize the added test effort and show to what extent the coverage of structural test criteria are maintained when components are integrated, in three representative component models. This enables focusing on testing the right aspects of the software at the right level of integration, and achieves cost reduction during testing — one of the most resource-consuming activities in software engineering.KeywordsTest ItemStructural TestTest CriterionExecution PathConcurrent ProgramThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The temperature control performance of a developed temperature feedback control system was experimentally investigated. The control system was based on a real-time temperature control of a cooling fluid. In particular, this study focused on the temperature control performance of a built-in motor spindle that used the developed temperature fedback control system. The built-in motor used in the study had water cooling jackets. The temperature of the built-in motor spindle was measured and feedback into the developed temperature feedback control system. Temperature control accuracy of the built-in motor spindle under steady state was then assessed. Furthermore, the effects of the time-variant changes in spindle rotation and ambient temperature on the performance of the temperature control system was investigated. The results of the experiments show that the temperature control accuracy of the built-in motor spindle under steady state condition was ±0.03°C. The temperature control performance of the built-in motor spindle under changes in the rotational speed of the spindle was examined. The experimental results show that the temperature change of the spindle could be suppressed to a maximum of approximately 0.3°C under transient state during sudden change in spindle speed. In addition, the effects of the changes in ambient and cooling water temperatures, which simulated actual environmental operating conditions, on the spindle temperature were investigated. The results show that the change in the spindle temperature could be suppressed by approximately less than ±0.1°C. These experimental results indicate that the developed temperature feedback control system achieved high temperature control accuracy and high response for the built-in motor spindle. In particular, the developed control system successfully controlled the time-variant change in the generated heat, thereby improving the thermal stability of the machine tool spindle.

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core x86 host machine for as many as 2,048 target processors whilst exhibiting minimal and near constant overhead, including memory considerations.

Development of a high-performance control system by decentralization with reflective memory on QUEST

In recent years, multi-core processors are becoming more and more common in embedded systems, offering higher performance than single-core processors and thereby enabling both computationally intensive embedded applications as well as the space-, weight-, and energy-efficient integration of software components. However, real-time applications, for which meeting certain deadlines must be guaranteed, do not profit as much from this transition. This is mainly due to interference between the processing cores of commercial-off-the-shelf multi-core processors at shared resources, hampering the predictability of task execution times. An effective approach to avoid this is running the critical tasks exclusively on one core while pausing execution on all other cores. This, however, reduces the overall system efficiency since parallel execution potential remains unused. In this work we present a novel approach to managing shared and exclusive execution in such systems. By on-line observation of the critical task progress via the on-chip trace infrastructure, we reduce the time of exclusive execution when it is safely possible and thereby increase the overall system efficiency. Using trace information allows for early detection of parallelization potential and does not require modifications to the critical application, which helps avoiding re-certification of the critical application. We present an implementation on a heterogeneous multi-processor system-on-chip using a state-of-the-art hypervisor for critical systems and evaluate its performance. Our results indicate that a performance gain of 37 % to 41 % over approaches focused on exclusive execution can be reached in low-interference situations.

Research on the interactions between risk, integration, and performance in supply chains (SCs) is increasingly attracting attention of researchers in recent years. Although risk usually has negative effects on performance, limited evidence has been provided to show whether companies differently exposed to operational risk (i.e., high, moderate, or low exposure) also have different levels of integration and operational performance. Therefore, this study aims to identify and characterize different profiles of operational risk (i.e., supply, manufacturing, and demand risks) between manufacturing companies along with considering contextual factors such as company size and industry type. Data are collected from the fourth round of the High Performance Manufacturing Project and subsequently analyzed by cluster analysis and analysis of variance (ANOVA). Three different clusters have been identified: Two clusters are moderately and highly impacted by operational risk, respectively, while the other cluster is almost not impacted by manufacturing risk but highly impacted by supply risk and demand risk. The results also indicate that companies with different profiles of operational risk have different levels of integration and operational performance. An important contribution of the current study is the development of a hypothesized framework of interactions between operational risk, integration, and operational performance to provide opportunities for further research.

Today, multi-core processors dominate server, desktop and notebook computer’s market. Such processors have been able to decrease power consumption and thermal challenges that designers face within single core processors. In order to improve multi-core processor’s performance, designers should choose the best set of cores based on power consumption and execution delay. In this paper, we study several architectures that are composed of a configurable number of cores. We use three cores with different levels of performance and power consumption. Then, we implement different configurations of a multi-core processor. In each configuration, which has a different set of cores, we run benchmarks with various numbers of simultaneous threads, from 1 up to 32. Power consumption and execution delay of each configuration has been measured. It has been shown that the best configuration is a heterogeneous multi-core processor that is composed of 16 cores in our bounded area. Then, we examined various ways that threads can be assigned to different cores in the best configuration. It is shown that for serial workloads the best choice is to use high performance cores, but in parallel workloads that consist of multiple threads, a mixture of cores with different performance levels gives the best performance.

We are interested in the resolution of the 3D Helmholtz equation for real applications. Solving this problem numerically is a computational challenge due to the large memory requirements of the matrices and vectors involved.For these cases, the massive parallelism of GPU architectures and the high performance at lower energy of the multicores can be exploited. To do a fair comparison between the benefit of accelerating the three-dimensional Helmholtz equation using GPU architectures and multicore platforms, this paper describes three different parallelization schemes on a multi-GPU cluster and also includes an evaluation of their performance. The three parallel schemes consist of:(1) using the multicore processors (CPU version), (2) using the GPU devices (GPU version); and (3) using a hybrid implementation which combines CPU cores and GPU devices simultaneously (hybrid version).Experimental results show that our hybrid implementation outperforms the other approaches in terms of performance.

Aimed at improving the resistance against power analysis attacks, a systematic and architectural design approach for multicore processors is proposed in this article and is demonstrated in an eight-core prototype platform with low performance overhead and hardware cost. In order to introduce randomness in both the time dimension and the amplitude dimension and make realignment extremely difficult, the proposed multicore platform leverages several methods together, such as random task scheduling (RTS), random insertion of operations (RIO), and frequency and phase randomization (FPR). Moreover, a power state monitoring and control (PSMC) scheme is proposed to defend against power analysis attacks by keeping enough background noises. A test chip of the proposed multicore processor is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS LP technology and can operate at up to 800 MHz with a 1.2-V supply. The Advanced Encryption Standard (AES) algorithm with these randomization methods is implemented on the processor. Measurement results show that the correlation power analysis (CPA) attacks and the power analysis attacks based on convolutional neural networks (CNNs) are unsuccessful even with 2 000 000 power traces when all the countermeasures are used.

Network interfaces for programmable NICs and multicore platforms