Bottom-up Verification for CMOS Photonic Linear Heterogeneous System

Due to the fact that the traditional Digital Electronic Technology (hereinafter referred to as DET) experiments bear sufficient reference material, elaborate design plan and complete design circuits (which makes it difficult for the students to design some experiments by themselves innovatively), but fail to bear enough experimenting methods, combined with the requirements raised by the competitions for experiment case teaching of elementary curriculums on electronic engineering and technique, in order to make some changes to the traditional experiment teaching, the paper innovated a new experiment case for the design of Rock-paper-scissors Game. In the design, two methods, Digital-integrated-circuit method and programmable-techniques method, are adopted to make it come true. When adopting digital-integrated-circuit method, right integrated circuit components will be employed according to the game-designing plan, using the software of Proteus to simulate it first, followed by debugging and testing of the hardware circuits on the bread board. The programmable-techniques method can describe the functions of the game on the development platform of the software of Quartus II by programming, adopting HDL (hardware description language). After right simulation, the programs will be downloaded onto FPGA experimental boxes or development board to realize the design of the game. The experimental case of Rock-paper-scissors Simulation Game is interesting and novel, which tends to stimulate the students to explore new world, study and innovate new things on their own. The adoption of the two methods will not only further enhance students’ knowledge application ability and engineer practice ability, but also help them better understand the difference of an experiment between the traditional and modern method, which will, in turn, understand the significance and value of programmable techniques in digital system designing.

A programmable counter/timer based on HDL (Hardware Description Language) design is proposed. The Intel 8254 is selected for defining the functionality and specifications of the programmable counter/timer. VHDL programs are first eveloped to emulate the functional operation of 8254. Next, the programs are verified by simulation using ModelSim. Then the hardware circuit is synthesized and analyzed. The experimental results show that, based on the proposed VHDL-driven design, a high complexity programmable counter/timer can be realized by programmable logic quickly and cost-effectively.

As embedded systems become integral in both academia and industry, hardware description languages are becoming a requisite part of Electrical and Computer Engineering curricula. The implementation of project-based learning in a freshman Digital Fundamentals course using an FPGA platform allows for greater engagement and learning through interesting and real-world projects. Through this approach, students strengthen the conceptual links between hardware description languages and circuit hardware while developing the ability to manage complex systems with multiple levels of abstraction. This paper discusses the implementation of three different application-driven projects on the Basys-3 trainer FPGA platform at the National University of Singapore and evaluates the effects of the key pedagogical differences. Both qualitative and quantitative assessment results are presented, showing how students perceived these projects and met the learning objectives.

This work presents a novel approach to integrating EDA tools and authoring their tutorials for basic electronic circuits education. The approach reflects the practical role of EDA tools in electronic circuits design while keeping hold of the fundamental theories behind basic circuits. Consequently, tutorials start playing a central role in addition to classical references. Therefore, this work also outlines a method that we have come up with at the Notre Dame University - Louaize, within the framework of the Cadence Academic Network, to author and continuously-improve these tutorials in a manner to maximize their effectiveness.

We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission speed and report on its performance.

Grating couplers are used to efficiently couple light from an optical fibre to a silicon waveguide as they allow light to be coupled into or out from any location on the device without the need for cleaving. However, using the typical surface relief grating fabrication method reduces surface planarity and hence makes further processing more difficult. The ability to manufacture high quality material layers on top of a grating coupler allows multiple active optical layers to be realized for multi-layer integrated optical circuits, and may enable monolithic integration of optical and electronic circuits on separate layers. Furthermore, the nature of the refractive index change may enable removal via rapid thermal annealing for wafer scale testing applications. We demonstrate for the first time a coupling device utilising a refractive index change introduced by lattice disorder. Simulations show 44% of the power can be extracted from the waveguide by using uniform implanted gratings, which is not dissimilar to the performance of typical uniform surface relief gratings currently used. Losses determined empirically, of 5.5 dB per coupler have been demonstrated.

Energy efficiency is one of the most critical aspects of todays information society. The most obvious benefits of being Green are reduced environmental impact and cost savings. Reducing energy consumption of electronic devices, circuits and heterogeneous systems, however, is not trivial. This requires the development of innovative energy-aware vertical design solutions and EDA technologies for next generations' nanoelectronics circuits and systems, and the related energy generation, conversion and management systems.

Recently, malfunctions by crosstalk between signal lines have become a problem in an electronic circuit which has been more densely organized and handles signals at higher frequencies. To prevent malfunctions due to these noises, it is important to find the relationship of the crosstalk with the materials and structures of the circuit board. Especially, as the density is increased, the use of multilayered configuration is increased so that the understanding of the crosstalk between interconnects arranged in a three‐dimensional fashion is increasingly more important.Usually, the analysis of crosstalk has been carried out by means of the equivalent circuit analysis. It is not easy to adjust the number of discretizations and the analysis between the three‐dimensional (3‐D) interconnects.In reference to the foregoing, this paper describes a crosstalk analysis between parallel microstrips by means of the finite‐difference time‐domain (FD‐TD) method which, among the 3‐D electromagnetic field analysis methods, requires small memory and computational time. Good agreement is confirmed between the thoretical and experimental results on the crosstalk waveforms and the crosstalk coefficient. Hence, the effectiveness of the FD‐TD method for the crosstalk analysis has been confirmed. It is believed that the FD‐TD method is extremely effective for analysis in the circuit design.

Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal-oxide-semiconductor (CMOS), gates. This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs. The design flow starts from a normal design in a hardware description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) or Verilog and provides a direct path to an SCA-resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. The basis for power analysis attack resistance is discussed. This paper describes how to adjust the library databases such that the regular single-ended static CMOS standard cells implement a dynamic and differential logic style and such that 20 000+ differential nets can be routed in parallel. This paper also explains how to modify the constraints and rules files for the synthesis, place, and differential route procedures. Measurement-based experimental results have demonstrated that the secure digital design flow is a functional technique to thwart side-channel power analysis. It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-mu m CMOS.

In order to improve the position control accuracy of industrial robots and solve the problems of poor real-time and reconfigurability of traditional motion controllers, a hardware implementation method for the motion mechanism and control system of multi-functional industrial robots is proposed. The video acquisition system is suitable for infrared detectors containing 4 channels or readout circuits in 4 channels. The video display system is compatible with the old AV/S-Video interface, and is also suitable for computer system video graphics array (VGA) analog video interface and high-definition video interface. Multimedia Interface (HDMI) digital high-definition video interface display terminal equipment. The hardware circuit of video acquisition and corresponding video interface image output is designed, including signal amplification circuit, analog-to-digital conversion circuit, video information buffer circuit, video display digital-to-analog conversion circuit, and interface hardware circuit, to realize the digitization of image information acquisition and image information. Display simulation, construct VGA, AV/S-Video, and HDMI timing sequence with hardware description language through Field programmable gate array (FPGA) to complete the display of corresponding terminal equipment. The experimental results show that the experimental data was substituted into the formula and the variance σ = 0.09 mm was found, indicating that the detection error of the system is less than 0.27 mm, which meets the detection requirements. Through the 3D contour reconstruction experiment of the workpiece, the expected function realization of each module is proved, and the feasibility of the system software and hardware system is verified. This design has good scalability and stability, reducing labor costs.

The method of cyclic redundancy check (CRC) was been used in the process of RFID communication adopts to ensure that the data was transfer correctly. The principle of CRC was been introduced. The design method about 16-bit CRC code was been gotten through the hardware circuit and hardware description language. And it was compatible with the serial and parallel two kinds of data streams. At the same time it was been verified correctly in RFID communication system. And the results are verified in the specified clock frequency in xc2vp4-6fg256 device in FPGA Xilinx kit using VI-IDL in RTL level. It with strong portability could extend to all CRC system.

Chapter 5 - “Traditional” Design Flows

Various electronic circuits such as inverters, choppers, cyclo-converters, SMPS used by industrial and domestic purposes are non-linear in nature, which makes the load current to be distorted, causing undesirable effects like heating, equipment damages, EMI related problems in power system. The active power filter (APF) is the best solution for eliminating the harmonics caused by the non-linear loads. This paper presents about a three-phase four-wire active power filter for power line conditioning to improve power quality in the distribution network and implementation of a digitally controlled APF. The active power filter is implemented with PWM based current controlled voltage source inverter (VSI).The switching signals for APF are generated through proposed three-level hysteresis current controller (HCC). The shunt APF system is modeled and investigated under different unbalanced non-linear load conditions using MATLAB program. The Controller Design using Hardware Description Language (VHDL or VERILOG) becomes independent of process technology. Synchronous reference frame (SRF) is used for generation of reference current. Both PI current algorithm and HCC are written in VHDL code and implemented using FPGA platform.

Development of integrated electronic and photonic circuits has led to distinctive data processing and transport capabilities. Scaling these devices to smaller and smaller dimension make these devices not only faster, power efficient and inexpensive components, but also lead to new challenges. A very important challenge is the growing size mismatch between photonic and electronic elements. To overcome this hurdle a new device technology, Plasmonic, is quickly becoming a dominant technology, which can facilitate information between integrated nanoscale components at optical frequencies by forming a medium between nano-electronic and micro-photonics. In this paper, Finite Difference Time Domain (FDTD), a universal brute-force numerical method in optics and electromagnetism is studied, which is used to analyze the plasmonic devices. FDTD method is aimed to solve Maxwell's equations by discretising both in space and time domain.

Control of the optical properties of nano‐plasmonic structures is essential for next‐generation optical circuits and high‐throughput biosensing platforms. Realization of such nano‐optical devices requires optical couplings of various nanostructured elements and field confinement at the nanoscale. In particular, symmetric coupling modes, also referred to as “dark modes”, have recently received considerable attention because these modes can confine light energy to small spaces. Although the coupling behavior of plasmonic nanoparticles has been relatively well‐studied, couplings of inverse structures, i.e., holes and pores, remain partially unexplored. Even for the most fundamental coupling system of two dipolar holes, comparison of the symmetric and anti‐symmetric coupling modes has not been performed. Here, we present a systematic study of the symmetric and anti‐symmetric coupling of nanopore pairs using cathodoluminescence by scanning transmission electron microscopy (CL‐STEM) and electromagnetic simulation. The nanopore samples were fabricated by colloidal lithography and film transfer by wet etching of the sacrificial layer. To achieve very close separation of nanopore pairs and to obtain high spatial resolution in STEM, we chose ultra‐thin, free‐standing film structures. For the measurement of single and coupled pairs of nanopores, 135 nm nanopores in an AlN(8 nm)/Au(16 nm)/AlN(8 nm) trilayer membrane were used (Figure 1b). With this sandwich layer structure, it is possible to obtain very thin and stable metal layers, even at high temperatures. For CL‐STEM measurement, 80 kV acceleration was used to avoid possible damage due to relatively high beam current. (5nA) Depending on the electron beam position it is possible to distinguish the symmetric and anti‐symmetric dipolar coupling modes.(Fig. 1) The observed symmetric coupling mode, approximated as a pair of facing dipoles, appeared at a lower energy than that of the anti‐symmetric coupling mode, indicating that the facing dipoles attract each other. The anti‐symmetric coupling mode splits into the inner‐ and outer‐edge localized modes as the coupling distance decreases. These coupling behaviors cannot be fully explained as simple inverses of coupled disks. Electromagnetic simulation by finite difference time domain (FDTD) also showed consistent coupling behaviors. Models of FDTD simulation showed that the inner‐ and outer‐edge anti‐symmetric modes become fully localized with minimal influence of the opposite edges as the coupling distance decreases. Symmetric and anti‐symmetric coupling modes are also observed in a short‐range ordered pore array (Fig. 2), where one pore supports multiple local resonance modes, depending on the distance to the neighboring pores.