Cavity Up and Stack Die Backside Failure Analysis for Thin Die and High Pin Count Devices

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.

The purpose of this paper is to present a conceptual approach and to make practical recommendations on how to improve the current Automatic Test Equipment (ATE) testing and maintenance capabilities by utilizing the existing cloud computing model to build a globally linked ATE maintenance system. The basic tenet of the ATE community is to support a multi-tiered maintenance concept which, in general, is a three tiered system that is composed of organizational maintenance (O-level), intermediate maintenance (I-level), and depot maintenance (D-level) organizations. The goal of the ATE is to (1) quickly and accurately detect and isolate each fault, (2) provide software tools for analyzing historical data, and (3) gather, manage, and distribute accurate and reliable maintenance information for the failed Unit Under Test (UUT). The ATE system should provide services that will (1) maintain a repository of information that will improve fault detection and isolation, allow for off-platform assessments, document failures, and help quantify corrective actions, (2) reduce false UUT pulls, and (3) reduce repair time by prompting repair procedures. Furthermore, the ATE system should provide additional services that will help optimize the time to diagnose problems by using collected failure information and by recommending entry points into the Test Program Set (TPS) software. It should also present information to the ATE maintainer to aid in informed repair decisions which could be in the form of pilot debrief results, platform Built In Test (BIT) results, O-level test outcomes and corrective actions, and maintenance and usage history of the platform and UUT. So, based on this definition of ATE maintenance the use of cloud computing can be used to provide services to improve the overall ATE testing throughput which will result in bottom line improvements to ATE life cycle costs. By using cloud computing, which is defined to be “a model for enabling ubiquitous, convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction”, users can develop cloud computing models that will provide access to application software and databases that can be used to build a globally linked ATE maintenance system. This paper will discuss the essential characteristics of the cloud computing models and define the various flavors of cloud offerings available to designers today. This paper will also analyze the cloud computing model to arrive at a conceptual approach that can be used to enhance the current ATE Testing and Maintenance capabilities. Practical recommendations will be discussed on how to transform the current ATE Testing and Maintenance capabilities into the specific cloud computing model offerings in order to help configure a globally linked ATE maintenance system.

A general defect modelling and simulation-assisted approach for fault isolation in failure analysis

Failure analysis (FA) could provide timely feedback to process optimization and solution paths for system failures; thus, it is critical for the development of advanced driver assistance systems (ADAS). In this chapter, failure analysis flows starting from systems or boards until components or packages and dice are introduced. Electrical fault isolation (FI) techniques designed to locate subtle defects inside complicated semiconductor devices are reviewed. Physical failure analysis approaches adopted to provide artifact free nanometer scale analysis are discussed. Material analysis methods assisting in thorough root cause investigation are presented. Non-destructive and high-resolution imaging tools with the potential of significantly shortening failure analysis through put time are demonstrated. Case studies are used to illustrate strategies and methodologies in ADAS failure analysis.

At-speed Logic BIST(Built-In Self-Test) has been embedded to the latest Cisco ASICs (Application Specific Integrated Circuit) and the test can be run on ATE (automatic test equipment) at probe and final test, as well as in-system during diagnostics, manufacturing, and even in the field. A fail state can be captured via JTAG interface. This paper presents a unified method of capturing LBIST failing flops for diagnostics. This allows failure analysis via scan-chain, design hierarchical, or physical view for fault isolation, yield, and maverick lot optimization. Most importantly, it provides a direct comparison of system test failure information with probe and final test.

Failure analysis (FA) is a basic and effective method to obtain the physical and failure information of electronic components and circuits. Most of these information can provide many useful evidences for prognostic and system health management (PHM) of electronic products. To obtain these information, many failure analysis techniques are used. This paper focuses on analyzing the relationship between FA techniques and PHM system. To test and verify the availability of the relationship between FA techniques and PHM system, a failure analysis case of an Intelligent Power Module (IPM) is used to study the relationship. This IPM contains six insulated gate bipolar transistors (IGBTs) and there are obvious burnout indications on most of them after failure. With the process of failure analysis, the key information, such as component's structure, sensitive parameters are identified. These results persuasively prove that FA techniques can provide much information to PHM system, including PoF and data-driven methods.

This paper describes two methods for testing high performance digital multichip modules (MCMs). The first technique provides a method for multiplexing automatic test system channels so that clock and data rates can be extended beyond the normal frequency limits of the Automatic Test Equipment (ATE). The multiplexing method has been successfully applied at rates up to 1.6 GHz using 200 MHz ATE. The second approach utilizes an electron beam probe system operating in the voltage contrast mode to measure electrical signals within the MCM. The e-beam probe can be used to supplement scan-based techniques for isolating faults. It can also be used for characterizing signal quality (rise-time, overshoot, crosstalk, reflections) and measurement of relative delays in high performance MCMs.

In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

This paper analyzes the through-put time and output of fault isolation and failure analysis (FI/FA) flows on state-of-the-art microprocessors. An average reduction in through-put time of 40% was demonstrated with a shortened FI/FA flow while still maintaining a high success rate. The direct FA/nano-probing flow which was utilized by up to around 90% of the fail cases omitted the optical fault isolation step and instead expanded the use of plasma FIB, nano-probing and electrical isolation techniques (such as diagnosis tools). The end result is shorter through-put time and higher FI/FA volume which is important in order to achieve a faster production ramp. In the paper two cases studies are presented to demonstrate the new efficient FI/FA techniques.

Stacked-chip scale package (S-CSP) is a new packaging technology introduced in the memory components market to effect chip miniaturization, a challenging trend in semiconductor assembly. The package is built by molding two stacked dice (Flash and SRAM) on bismaleimide triazine (BT) substrate. As this novel packaging technology offers solution to the challenge, it also poses complexity in the field of failure analysis in cases that the bottom die is the interest. Deprocessing these stacked dice while maintaining the functionality of the bottom die will be explained in detail. Prior the conduct of failure analysis (FA) and fault isolation (FI), deprocessing the failing unit containing only one die normally consists of chemical decapsulation. S-CSP sample preparation also adheres to this treatment in case the top die is the aim for analysis. On the other hand, if the concern shifts to the bottom die, sequential techniques involving precision polishing to die-to-die adhesive layer, chemical etching of adhesive and residual molding compound, and rebonding the bottom die on ceramic interposer, are employed. With the rebonded S-CSP bottom die, fault isolation could be performed further. This paper will also feature the mechanism behind the blown-up failure, a power test failure in memory devices, encountered during the package development when two types of die-to-die adhesives were selected and used. Consistent with the results of electrical characterization suggesting that S-CSP bottom die as the failing die, passivation damage is uncovered on the bottom die upon separation of the stacked dice. Material comparison points out that the hard, angular glass fillers of the die-to-die adhesive induce the damage. Polymer-filled adhesive performs better than the glass-filled adhesive as indicated by the results of the package characterization. Generally, this case exemplifies a packaging material-related failure. Moreover, the paper could serve as a reference material in the event that feasibility of packaging non-memory components in S-CSP is to be evaluated. The developed methodology of recovering the S-CSP bottom die would be a keystone in proacting for its FA readiness.

This research project aims to expand the capability of current US Navy Automated Test Equipment (ATE) family of testers known as the Consolidated Automated Support System (CASS). Industry research is now focused on breaking the historical construct of test equipment. Advances in the field of Synthetic Instruments have opened the door to test avionics in new ways. Every year new capabilities are developed using core hardware and increasingly capable software modules to create complex waveforms. This research creates a Digital Radio Frequency Memory (DRFM) Synthetic Instrument that can be programmed to perform a wide array of low latency Radio Frequency (RF) tests. Synthetic Instruments are defined as a concatenation of hardware and software modules used in combination to emulate a traditional piece of electronic instrumentation. This Synthetic Instrument couples high speed Analog-to-Digital Converters (ADC) to high speed Digital-to-Analog Converters (DAC) with Field Programmable Gate Arrays (FPGA) in between for digital signal processing. An RF front end is used to down convert the RF to baseband where it is sampled, modified, and up converted back to RF. The FPGA performs Digital Signal Processing (DSP) on the signal to achieve the desired output. Application of this DRFM in automated testing is demonstrated using a Reconfigurable Transportable Consolidated Automated Support System (RTCASS) tester at Naval Air Systems Command (NAVAIR) Jacksonville, FL. The Unit Under Test (UUT) is an ALQ-162 Defensive Electronic Countermeasures (DECM) receiver-transmitter. Ultra-low latency signals are generated to simulate enemy jamming stimulus. As the ALQ-162 detects and responds to the input, the DRFM switches to a new frequency. The time taken by the ALQ-162 to acquire, respond, and re-acquire is measured. This test confirms the internal Yttrium Iron Garnet (YIG) oscillator meets slew specifications. Currently Navy ATE can only test RF units using high latency steady state tests. This research project developed a supplemental unit that can be added to the VXI chassis in the CASS family of testers and conduct ultra-low latency active tests. The instrument acts as hardware-in-the-loop to perform real-time tests including a new capability to measure jamming response time from DECM avionics. Demonstrated performance capabilities include: latency <; 100 ns, output Spurious-Free Dynamic Range (SFDR) > 80 dBc, input SFDR > 60 dBc, frequency tuning resolution <; 2 Hz, and frequency settling time <; 0.5 ns. New RF capabilities developed by this effort parallel similar research ongoing for digital test instruments like the Teradyne High Speed Subsystem. Incorporating this Digital RF Memory synthetic instrument into current and future ATE will improve readiness and supportability of the fleet. Improvements demonstrated by this research project will expand the type and quantity of assets able to be tested by current and future ATE.

SummaryThis paper proposes an integrated actuator and sensor active fault‐tolerant model predictive control scheme. In this scheme, fault detection is implemented by using a set‐valued observer, fault isolation (FI) is performed by set manipulations, and fault‐tolerant control is carried out through the design of a robust model predictive control law. In this paper, a set‐valued observer is used to passively complete the fault detection task, while FI is actively performed by making use of the constraint‐handling capability of robust model predictive control. The set‐valued observer is chosen to implement fault detection and isolation (FDI) because of its simple mathematical structure that is not affected by the type of faults such as sensor, actuator, and system‐structural faults. This means that only one set‐valued observer is needed to monitor all considered actuator and sensor statuses (health and fault) and to carry out the fault detection and isolation task instead of using a bank of observers (each observer matching a health/fault status). Furthermore, in the proposed scheme, the advantage of robust model predictive control is that it can effectively deal with system constraints, disturbances, and noises and allow to implement an active FI strategy, which can improve FI sensitivity when compared with the passive FI methods. Finally, a case study based on the well‐known two‐tank system is used to illustrate the effectiveness of the proposed fault‐tolerant model predictive control scheme. Copyright © 2016 John Wiley &amp; Sons, Ltd.

Hard disk failure is a serious problem in term of product quality and credibility to customers. All hard disk drive companies need to be aware and address how to get rid of failure and prevent the repeat of the problem in their products. The quality of failure analysis process depends on the person who has most experience. It would not be so efficient if the company has no experienced person to perform the analysis. A knowledge management system can store the knowledge of experienced engineers. It can help new engineers to learn the craft. It would reduce a knowledge gap issues and bring up efficiency for failure solving process. This paper presents a design and implementation of knowledge management system for failure analysis in hard disk with case-based reasoning. The existing cases are stored and a new case can be compared to the existing one in order to retrieve the relevant existing knowledge to help the analysis. Once the new case is solved, it can be stored to aid the future cases. A prototype of the system has been implemented and the assessment of user satisfaction shows that it can improve the failure analysis process effectively.

This paper describes the incorporation of a Commercial-Off-The-Shelf (COTS) video stimulus instrument in the Navy's Consolidated Automated Support System (CASS) ATS. Included are COTS instrument selection, CASS software modifications, CASS modifications, and product enhancements, which evolved out of the effort. The video stimulus requirement of the U.S Navy's Consolidated Automated Support System (CASS) was fulfilled via the integration of a commercial instrument into the CASS. The effort involved product research, selection, and testing; mechanical and electrical design and testing; software engineering; integration; and fielding. The major component (a commercial video stimulus instrument) was selected. CASS software was modified to support an ATLAS interface to the instrument. The CASS ATS was modified to accommodate the instrument; this modification required mechanical design testing. The video signal path (instrument to CASS interface) was developed; and the product was enhanced to provide rudimentary animation capabilities in support of infrared tracking systems. The focus of the paper is product selection and requirements matching; software development and integration with the existing product; system testing and calibration; retrofitting of fielded systems. A brief section focuses on enhancements (beyond the original scope) that evolved from capabilities of the COTS instrument.

Semiconductor trends as embodied in the International Technology Roadmap for Semiconductors (ITRS) provides a guide for the challenges facing the failure analysis community. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are driven primarily by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The likely industry paths for addressing these challenges are discussed. The International Sematech Product Analysis Forum (Joseph et al, 2000) has identified ten primary challenges for the future of the failure analysis in the semiconductor industry: localization and electrical characterization; deprocessing techniques for new materials; system-on-a-chip; imaging of small defects and structures; detection and characterization of nonvisual defects; verification and test; globally dispersed entities as virtual factory; fault isolation and simulation software; cost of failure analysis; complexity and volume of data. These challenges have been correlated to the Technology Working Group Difficult Challenge table in the ITRS.