Using failure analysis techniques to identify key information of PHM

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Failure analysis on 14 nm FinFET devices with ESD CDM failure

In an era where the complexity and cost of Failure Analysis tools and techniques is rapidly expanding, it is easy sometimes to lose sight of the basic tool and technique required for successful root-cause analysis. That technique is intellectual curiosity and the tool is the human brain. This paper will describe a simple methodology to insure that this tool and technique are properly engaged either concomitant with or in the absence of state-of-the-art instrumentation and computation. Two simple case studies will be used to illustrate where the Failure Analysis process can easily go awry without proper attention to detail, and, conversely, from too much attention to detail.

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

TrenchMOS FET devices fabricated vertically instead of conventional horizontal POWERMOS devices. Conventional failure analysis techniques have shown difficulty in identifying the failing location if the defect happens at the bottom of trench. Different failure analysis techniques have been developed to analyze the low yield wafers. This paper demonstrates the use of various failure analysis techniques to isolate the defective location and assisting Fab process team to resolve the issue and improve yield.

Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

This paper examines one of the common modes of structural failure in multichip BGAs, determines its locations within the package structure, relates it to the stresses generated in the reliability tests under which it occurs, and by Finite Element simulations, determines an explanation for the failure, and finally proposes a method to avoid this failure mechanism. Several designs of multichip BGA substrates were manufactured and production silicon assembled into them. These were all 14/spl times/22 mm 119 ball PBGA. These were subjected to a set of package reliability tests, until some units failed electrical test. The failed units were analysed and the physical location and shape of the failure was determined in many cases. From this information, the mechanical mode of failure for each unit was determined. In addition there was sufficient information in some of the analyses to provide definite suggestions as to the mechanism of failure. Meanwhile, Finite Element Analysis was performed using simplified representations of the multichip BGAs, in order to find the locations of highest stress, and the expected modes of failure. This data was matched to the failure modes found in the physical analysis. Some novel failure analysis techniques were used to expose the damage in the failed units. A particular failure mode occurred frequently in temperature cycle, and the sites of failure were located by failure analysis. The failure was due to open circuit in the copper tracks in the top layer of the substrate caused by cracking in the solder resist directly underneath the edge of the die attach fillet. Finite element analysis was carried out and the location of the actual failures was found to be a local zone of high tensile stress in the solder resist.

Root cause failure analysis of lithium-ion batteries provides important feedback for cell design, manufacture, and use. As batteries are being produced with larger form factors and higher energy densities, failure analysis techniques must be adapted to characteristics of the specific batteries. This paper will discuss the significance of melted copper in lithium-ion battery cells that have experienced thermal runaway and how the interpretation of such evidence has evolved over time. Specialized testing techniques that may prove helpful in determining the root cause of battery failures will also be described.

CADless laser assisted methodologies for failure analysis and device reliability

Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

Due to practical limitations in the manufacturing of power semiconductor dies, high power modules are composed of several dies in parallel in order to meet the desired load current requirements. With careful attention to the design, modern insulated gate bipolar transistor (IGBT)-based power modules feature relatively balanced current distribution amongst the parallel dies. However, owing to the increased switching speeds of wide bandgap devices, i.e., silicon carbide (SiC), it is challenging to design the package to achieve both low-loss and balanced operation. In this article, a technique is proposed where the individual dies in a multidie power module can be selectively driven by a closely integrated gate buffer. Amongst the benefits achieved by selectively driving the die gates, a profiling of the power loss within the intelligent power module is enabled. Furthermore, a practical technique to estimate the individual die temperatures is presented, and using the same method, the on-state voltage of the power module during load current conduction can be estimated. Finally, it is experimentally demonstrated that the combination of individual junction temperature estimation and the selective gate driving can be used to increase the power density of the power module by better utilizing the component dies.

This paper describes the characteristics of a new IGBT based intelligent power module (IPM) designed for 15KW to 60KW industrial motor drive applications. For the first time HVIC (High Voltage Integrated Circuit) technology has been adopted in this power range in order to provide enhanced diagnostic and protection functions while simplifying or eliminating peripheral circuits that were previously required. The main additions compared to existing IPMs include: (1) level shifting of control inputs to eliminate the need for isolated gate drive channels, (2) User adjustable switching speed, (3) Error mode identification feedback, (4) Operating temperature information, (5) Shoot-through prevention interlock, and (6) Boot-strap circuit with auxiliary support to eliminate the need for multiple isolated power supplies. This paper will describe the implementation of these functions and explain the system level benefits.

Guide for authors — Geo-Science Publications

Focused ion beam (FIB) is commonly used as a standard machining technique in failure analysis, quality control, reverse engineering, material research, and so on, for the samples having microstructures and nanostructures. FIB combined with time‐of‐flight secondary ion mass spectrometry (TOF‐SIMS), so‐called FIB‐TOF, has attracted attention as a method to determine the three‐dimensional (3D) chemical distributions of complex samples. In general, a highly focused Ga + ion beam is used for FIB, however, the FIB‐milled area is limited and it was difficult to expand the Ga‐FIB to hundreds of micron length scale for sample fabrication. In order to overcome the drawback, we proposed the Bi‐FIB approach for large scale sample cross‐sectioning. Although the possibility of Bi‐FIB has been reported, there were almost no performance examinations as well as practical applications. In this study, therefore, the authors summarize the comparison of milling rate and milling damage between Ga‐FIB and Bi‐FIB. As a result, it was found that Bi‐FIB can provide a higher milling rate with thinner milling damage. Finally, the Bi‐FIB approach was applied to the interfacial analysis of all‐solid‐state battery (ASSB) material. With this approach, the detailed chemical distributions at the interface were discovered, leading to the better understanding of battery behaviors.

The greatest concern on MOB devices is the physical integrity of the gate oxide. Leakage paths and/or shorts through defect sites in the oxide are a major device reliability problem. Optical microscopy is tedious and often does not resolve the defects. With this in mind, copper decoration techniques were developed that could reveal oxide failures sites down to 0.1?m size. The technique has isolated various failure mechanisms on MOS devices. This failure analysis capability has enhanced the ability to control the MOS process.